（精選）基于FPGA的Verilog-HDL數(shù)字鐘設計--

1、基于FPGA的Verilog HDL數(shù)字鐘設計專業(yè)班級 姓 名 學 號 一、實驗目的1.掌握可編程邏輯器件的應用開發(fā)技術(shù) 設計輸入、編譯、仿真和器件編程；2.熟悉一種EDA軟件使用；3.掌握Verilog設計方法； 4.掌握分模塊分層次的設計方法； 5.用Verilog完成一個多功能數(shù)字鐘設計; 6.學會FPGA的仿真。二、實驗要求² 功能要求：利用實驗板設計實現(xiàn)一個能顯示時分秒的多功能電子鐘，基本功能：1) 準確計時，以數(shù)字形式顯示時、分、秒，可通過按鍵選擇當前顯示時間范圍模式；2) 計時時間范圍 00:00:0023:59:593) 可實現(xiàn)

2、校正時間功能；4) 可通過實現(xiàn)時鐘復位功能：00:00:00擴展功能：5) 定時報：時間自定(不要求改變)，鬧1分鐘(1kHz)-利用板上LED或外接電路實現(xiàn)。仿廣播電臺正點報時：XX:59:51,53,55,57(500Hz);59(1kHz) -用板上LED或外接6) 報整點時數(shù)：XX:00:00.5-XX.5(1kHz)，自動、手動-用板上LED或外接7) 手動輸入校時；8) 手動輸入定時鬧鐘；9) 萬年歷；10) 其他擴展功能；² 設計步驟與要求：1) 計算并說明采用Basys2實驗板時鐘50MHz實現(xiàn)系統(tǒng)功能的基本原理。2) 在Xilinx ISE13.1 軟件中，利用層次

3、化方法，設計實現(xiàn)模一百計數(shù)及顯示的電路系統(tǒng)，設計模塊間的連接調(diào)用關(guān)系，編寫并輸入所設計的源程序文件。3) 對源程序進行編譯及仿真分析（注意合理設置，以便能夠在驗證邏輯的基礎(chǔ)上盡快得出仿真結(jié)果）。4) 輸入管腳約束文件，對設計項目進行編譯與邏輯綜合，生成下載所需.bit文件。5) 在Basys2實驗板上下載所生成的.bit文件，觀察驗證所設計的電路功能。3、 實驗設計功能說明：實現(xiàn)時鐘，時間校時，鬧鈴定時，秒表計時等功能1. 時鐘功能：完成分鐘/小時的正確計數(shù)并顯示；秒的顯示用LED燈的閃爍做指示；時鐘利用4位數(shù)碼管顯示時分；2. 鬧鐘定時：實現(xiàn)定時提醒及定時報時，利用LED燈代替揚聲器發(fā)出報時

4、聲音；3. 時鐘校時：當認為時鐘不準確時，可以分別對分鐘和小時位的值進行調(diào)整；4. 秒表功能：利用4個數(shù)碼管完成秒表顯示： 可以實現(xiàn)清零、暫停并記錄時間等功能。秒表利用4位數(shù)碼管計數(shù)；方案說明：本次設計由時鐘模塊和譯碼模塊組成。時鐘模塊中50MHz的系統(tǒng)時鐘clk分頻產(chǎn)生一個1Hz的使能控制信號enable，并以此產(chǎn)生1s的脈沖second_en以實現(xiàn)每秒計時，控制各個模式下的計數(shù)顯示。由模式控制信號選擇當前數(shù)碼管顯示哪個狀態(tài)：mode=00，時鐘常規(guī)顯示狀態(tài)，mode=01，鬧鈴定時狀態(tài)，mode=10，時鐘校時狀態(tài)，mode=11，秒表計時狀態(tài)；時鐘：利用count，smin0，smin1

5、，shour0，shour1的計數(shù)來實現(xiàn)，具體情況見程序； 校時：當turn=1時，調(diào)整分位smin1、smin0；當turn=0時，調(diào)整小時位shour1、shour0；鬧鈴：當turn=1時，調(diào)整分位amin1、amin0；當turn=0時，調(diào)整小時位ahour1、ahour0；秒表：當pause=0時，開始計時；當pause=1時，暫停。4、 實驗代碼時鐘模塊module clock(clk, clr, pause, turn, mode, sec, min1, min0, hour1, hour0, alert, LD_alert );input clk; /時鐘信號(50MHz)in

6、put clr; /清零鍵input pause; /秒表暫停鍵input turn; /調(diào)整分還是小時位的控制input 1:0mode; /決定時鐘顯示功能狀態(tài)output sec; /接發(fā)光二極管output 3:0min1; /用于輸出接數(shù)碼管4output 3:0min0; /用于輸出接數(shù)碼管3output 3:0hour1; /用于輸出接數(shù)碼管2output 3:0hour0; /用于輸出接數(shù)碼管1output alert; /接發(fā)光二極管，代替蜂鳴器output LD_alert; /當鬧鈴設定后，發(fā)光二極管顯示wire sec; /秒位顯示wire LD_alert; /用于鬧

7、鈴存在時的提醒顯示/wire clk1; /時鐘1s/wire clk2; /時鐘100ms，用于秒表最小計時單位/wire clr1;reg 3:0min1; /常規(guī)顯示reg 3:0min0; /常規(guī)顯示reg 3:0hour1; /常規(guī)顯示reg 3:0hour0; /常規(guī)顯示reg 3:0smin1; /校時reg 3:0smin0; /校時reg 3:0shour1; /校時reg 3:0shour0; /校時reg 3:0amin1; /鬧鈴reg 3:0amin0; /鬧鈴reg 3:0ahour1; /鬧鈴reg 3:0ahour0; /鬧鈴reg 3:0mmin1; /秒表r

8、eg 3:0mmin0; /秒表reg 3:0mhour1; /秒表reg 3:0mhour0; /秒表reg alert; /當鬧鈴到時高電平輸出reg 7:0count;reg 24:0counter;reg enable;reg en1,en2;wire second_en;always (posedge clk) /generate 1sbegin if (clr) begin counter = 0; enable = 0; end else begin counter = counter +1; if (counter = 25'd249) / 仿真時可將閘門信號設為0.0

9、0001s，加快仿真速度/ if (counter = 25'd24999999) / 執(zhí)行設計時將閘門信號改回為1s begin enable = enable; counter = 25'd0; end endendalways (posedge clk) /?begin if (clr) begin en1 <= 1'b0; en2 <= 1'b0; end else begin en1 <= enable; en2 <= en1; end endassign second_en = (!en1) && (en2);

10、always (posedge clk) begin if(clr) begin amin1<=0; amin0<=0; ahour1<=0; ahour0<=0; smin1<=0; smin0<=0; shour1<=0; shour0<=0; mmin1<=0; mmin0<=0; mhour1<=0; mhour0<=0; count<=0; end else if (second_en) begin count<=count+1; / if(mode=2'b01) /鬧鈴調(diào)時狀態(tài) if(tur

11、n=1) /當turn為高電平時調(diào)整分位 if(amin1=5)&&(amin0=9) begin amin1<=0; amin0<=0; end else if(amin0=9) begin amin1<=amin1+1; amin0<=0; end else amin0<= amin0+1; else /當turn為低電平時調(diào)整小時位 if(ahour1=2)&&(ahour0=3) begin ahour1<=0; ahour0<=0; end else if(ahour0=9) begin ahour1<=

12、ahour1+1; ahour0<=0; end else ahour0<=ahour0+1; / if(mode=2'b10) /時鐘調(diào)時狀態(tài) if(turn=1) /當turn為高電平時調(diào)整分位 if(smin1=5)&&(smin0=9) begin smin1<=0; smin0<=0; end else if(smin0=9) begin smin1<=smin1+1; smin0<=0; end else smin0<=smin0+1; else /當turn為低電平時調(diào)整小時位 if(shour1=2)&&

13、amp;(shour0=3) begin shour1<=0; shour0<=0; end else if(shour0=9) begin shour1<=shour1+1; shour0<=0; end else shour0<=shour0+1; else /以下是常規(guī)顯示begin if(count=59) begin count<=0; smin0<=smin0+1; if (smin0=9) begin smin0<=0; smin1<=smin1+1; if (smin1=5) begin smin1<=0;shour0

14、<=shour0+1;if (shour0=3)begin shour0<=0; shour1<=shour1+1; if (shour1=2) shour1<=0;end endendendend / if(mode=2'b11) begin /秒表計時狀態(tài) if(pause=0) /當pause為低電平時開始計時 begin mmin0<=mmin0+1; if(mmin0=9) begin mmin0<=0; mmin1<=mmin1+1; if(mmin1=9) begin mmin1<=0; mhour0<=mhour0+

15、1; if (mhour0=9) begin mhour0<=0;mhour1<=mhour1+1;if (mhour1=9) mhour1<=0; end endend endend end end assign LD_alert=(amin1|amin0|ahour1|ahour0)?1:0; /當鬧鈴有定時后LD_alert發(fā)光以示鬧鈴已定assign sec=enable; /將秒針接到LED燈always(posedge clk) begin if(clr) alert<=0; else if(amin1=smin1)&&(amin0=smin

16、0)&&(ahour1=shour1)&&(ahour0=shour0) alert<=1; /對鬧鈴做檢查，時間到時發(fā)光 else alert<=0; end/以下為選擇顯示模塊always (posedge clk)begin if(clr) begin min1<=0; min0<=0; hour1<=0; hour0<=0; endelse begin case(mode) 2'b01: begin /mode=01時，顯示鬧鈴模塊 min1<=amin1; min0<=amin0; hour1&l

17、t;=ahour1; hour0<=ahour0; end 2'b10: begin /mode=10時，顯示校時模塊 min1<=smin1; min0<=smin0; hour1<=shour1; hour0<=shour0; end 2'b11: begin /mode=11時，顯示秒表模塊 min1<=mmin1; min0<=mmin0; hour1<=mhour1; hour0<=mhour0; end 2'b00: begin /其他狀態(tài)，顯示普通時鐘模塊 min1<=smin1; min0<

18、;=smin0; hour1<=shour1; hour0<=shour0; end endcase end end endmodule譯碼模塊module display(q,ctr,h1,h0,m1,m0,clk,reset);output6:0q;output3:0 ctr;input3:0 h1,h0,m1,m0;input clk,reset;reg6:0 q;reg25:0 count;reg3:0 temp;reg3:0 scan;/delay yanshi(clk,clk2);always (posedge clk) begin if (reset) begin c

19、ount = 0; end else begin count = count +1; endendalways (posedge clk ) /Seg Scan begin if(reset)begin scan<=4'b0000;endelse case(count1:0) / 仿真時將掃描信號頻率加快1000倍/ case(count11:10) / 執(zhí)行設計時將掃描頻率改回 2'b00: scan<=4'b0111; 2'b01: scan<=4'b1011; 2'b10: scan<=4'b1101; 2&

20、#39;b11: scan<=4'b1110; endcaseendassign ctr = scan;always (posedge clk) /Seg Scanbegin if(reset)begin temp<=4'b0000;endelse case(count1:0) / 仿真時將掃描信號頻率加快1000倍/ case(count11:10) / 執(zhí)行設計時將掃描頻率改回 2'b00: temp<=h1; 2'b01: temp<=h0; 2'b10: temp<=m1; 2'b11: temp<=m

21、0; endcaseendalways (posedge clk) /數(shù)碼管譯碼begin if(reset)begin q<=7'b0000000;endelse case(temp)4'd0:q<=7'b0000001; /04'd1:q<=7'b1001111; /14'd2:q<=7'b0010010; /24'd3:q<=7'b0000110; /34'd4:q<=7'b1001100; /44'd5:q<=7'b0100100; /54&

22、#39;d6:q<=7'b0100000; /64'd7:q<=7'b0001111; /74'd8:q<=7'b0000000; /84'd9:q<=7'b0000100; /9default:q<=7'b0000001; endcaseendendmoduleUCF文件NET "clk" LOC = "B8" # 50M# Pin assignment for DispCtl# Connected to Basys2 onBoard 7q displayNE

23、T "q<6>" LOC = "L14" # Bank = 1, Signal name = CANET "q<5>" LOC = "H12" # Bank = 1, Signal name = CBNET "q<4>" LOC = "N14" # Bank = 1, Signal name = CCNET "q<3>" LOC = "N11" # Bank = 2, Signal nam

24、e = CDNET "q<2>" LOC = "P12" # Bank = 2, Signal name = CENET "q<1>" LOC = "L13" # Bank = 1, Signal name = CFNET "q<0>" LOC = "M12" # Bank = 1, Signal name = CG#NET "dp" LOC = "N13" # Bank = 1, Signal na

25、me = DPNET "ctr<3>" LOC = "K14" # Bank = 1, Signal name = AN3NET "ctr<2>" LOC = "M13" # Bank = 1, Signal name = AN2NET "ctr<1>" LOC = "J12" # Bank = 1, Signal name = AN1NET "ctr<0>" LOC = "F12" #

26、Bank = 1, Signal name = AN0NET "reset" LOC = "N3" # Bank = 2, Signal name = SW7NET "mode<1>" LOC = "E2" # Bank = 3, Signal name = SW6NET "mode<0>" LOC = "F3" # Bank = 3, Signal name = SW5NET "turn" LOC = "G3"

27、 # Bank = 3, Signal name = SW4NET "pause" LOC = "B4" # Bank = 3, Signal name = SW3NET "LD_alert" LOC = "P7" ; # Bank = 3, Signal name = LD2NET "alert" LOC = "M11" ; # Bank = 2, Signal name = LD1NET "sec" LOC = "M5" ; # B

28、ank = 2, Signal name = LD0testbenchmodule tb_test;/ Inputsreg clk;reg reset;reg 1:0 mode;reg turn;reg pause;/ Outputswire 6:0 q;wire 3:0 ctr;wire sec;wire alert;wire LD_alert;/ Instantiate the Unit Under Test (UUT)clk uut (.clk(clk), .reset(reset), .mode(mode), .turn(turn), .pause(pause), .q(q), .ct

29、r(ctr), .sec(sec), .alert(alert), .LD_alert(LD_alert); parameter PERIOD = 10; always begin clk = 1'b0; #(PERIOD/2) clk= 1'b1; #(PERIOD/2); endinitial begin/ Initialize Inputsreset = 1;mode = 2'b00;turn = 0;pause = 0;/ Wait 100 ns for global reset to finish#500;reset = 0;mode = 2'b00;turn = 0;#600000;mode = 2'b01;turn = 0;#60000;mode = 2'b01;turn = 1;#60000;mode = 2'b10;turn = 0;#60000;mode = 2'b10;turn = 1;#60000;mode = 2'b11;#60000;pause = 1;#60000;reset = 1;