組合邏輯控制單元設計

1、一、實驗課題實驗要求：按照題目要求用硬布線（組合邏輯）控制法設計一個簡單模型機的控制單元CU（微操作信號產生電路），決定外部的端口（名稱、有效電平）和內部各元件的連接，畫出系統(tǒng)框圖和邏輯圖，設計仿真數據，用VHDL編程和仿真。主要元件設計：1指令譯碼器功能要求：3-8譯碼器。2控制單元 功能要求：假設該模型機有8條不同類型的指令。包括：算術運算、邏輯運算、移位、數據傳送、訪存操作、轉移等。根據每條指令的功能和時序，分析其執(zhí)行過程中需要在各個階段產生的全部微操作，導出產生這些微操作控制信號的邏輯。 3用層次結構設計的方法設計一個控制單元CU（微操作控制信號產生電路）。包括指令譯碼器和控制單元。功

2、能要求：能夠正確產生8條不同指令在執(zhí)行過程中（每個機器周期、每拍）發(fā)出的全部微操作。二、邏輯設計寫該實驗的邏輯設計，包括：頂層系統(tǒng)框圖，下層各主要元件的系統(tǒng)框圖。頂層和下層各主要元件的端口（引腳）描述：端口名稱、功能、有效電平、位數等。邏輯圖，必須在圖中清楚地標出每個內部連接線的Signal（與VHDL程序中的Signal一致）。根據所用的描述方式，可能還需要有：真值表/功能表/邏輯函數等。1、3-8譯碼器：系統(tǒng)框圖：Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 3-8譯碼器 S A2 A1 A0S是工作信號，當S=1時，3-8譯碼器工作；當S=0時，3-8譯碼器不工作。A是輸入信號，Y是輸

3、出信號S A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 1 0 0 0 0 0 0 0 0 0 0 1 加法1 0 0 1 0 0 0 0 0 0 1 0 與1 0 1 0 0 0 0 0 0 1 0 0 或1 0 1 1 0 0 0 0 1 0 0 0 左移1 1 0 0 0 0 0 1 0 0 0 0 右移1 1 0 1 0 0 1 0 0 0 0 0 數據傳送1 1 1 0 0 1 0 0 0 0 0 0 取數1 1 1 1 1 0 0 0 0 0 0 0 無條件轉移0 × × × 0 0 0 0 0 0 0 0 Y(0)<=S a

4、nd (not A(2) and (not A(1) and (not A(0);Y(1)<=S and (not A(2) and (not A(1) and A(0);Y(2)<=S and (not A(2) and A(1) and (not A(0);Y(3)<=S and (not A(2) and A(1) and A(0);Y(4)<=S and A(2) and (not A(1) and (not A(0);Y(5)<=S and A(2) and (not A(1) and A(0);Y(6)<=S and A(2) and A(1)

5、and (not A(0);Y(7)<=S and A(2) and A(1) and A(0);2、控制單元：設計過程：把每條指令的實現(xiàn)分成取指令、分析指令、執(zhí)行指令三個步驟，每一步由一個機器周期實現(xiàn)，一條指令的實現(xiàn)需要三個機器周期，即M1（取指周期）、M2（分析周期）、M3（執(zhí)行周期）；每個機器周期由三個節(jié)拍組成，即T0、T1、T2。如下圖所示：機器周期節(jié)拍T0T1T2M0M1M21、加法指令：寄存器R1中的一個數與寄存器R0中的一個數相加，結果放在R1中。即實現(xiàn)（R0）+（R1）R12、與指令：寄存器R1中的一個數與寄存器R0中的一個數，結果放在R1中。即實現(xiàn)（R1）and (R0

6、) R1 3、或指令：寄存器R1中的一個數或寄存器R0中的一個數，結果放在R1中。即實現(xiàn)（R1）or (R0) R1 4、邏輯左移指令：寄存器R1中的數左移，移動位數存放在寄存器R0中，結果放在R1中。即實現(xiàn)（R1）R15、邏輯右移指令：寄存器R1中的數左移，移動位數存放在寄存器R0中，結果放在R1中。即實現(xiàn)（R1）R16、數據傳送指令：寄存器R0中的數據送到寄存器R1中。即實現(xiàn)（R0） R1。7、取數指令：取出存儲器中的一個數（地址在寄存器R0中）送到寄存器R1中。即實現(xiàn)（R0）（R1）8、無條件轉移指令：寄存器R1中的地址送到PC中。即實現(xiàn)（R1） PC8條指令的微操作如下表所示，以教材P

7、122的CPU控制圖（省去了M/、ADS）為例：由于每條指令取指周期的微操作是一樣的，所以可以先設計取指周期微操作的節(jié)拍安排。取指周期：T0：PCAB，W/=0T1：DBIRT2：PC+1T0T1T2加法M1rs1GR(rs1) ALUrd GR(rd) ALUM2+ALU GR與M1rs1GR(rs1) ALUrd GR(rd) ALUM2ALU GR或M1rs1GR(rs1) ALUrd GR(rd) ALUM2ALU GR左移M1rs1GR(rs1) ALUrd GR(rd) ALUM2ALU GR右移M1rs1GR(rs1) ALUrd GR(rd) ALUM2ALU GR數據傳送M1

8、rs1GR(rs1) ALUM2+ALU GR取數M1rs1GR(rs1) ALU+ALUAR，ARABW/=0DBDRM2DRALU+ALU GR無條件轉移M1rs1 GR(rs1) ALUM2+ALUPCd7 d0 m2 m1 m0 t2 t1 t0 控制單元 q18 q0系統(tǒng)框圖：工作周期節(jié)拍微操作命令加法與或左移右移數據傳送取數無條件轉移ADDANDORSALSARMOVLDAJMP取指周期 T0PCAB11111111W/=011111111T1DBIR11111111T2PC+111111111分析周期T0rs1GR11111111(rs1)ALU11111111+1T1ALUAR

9、1ARAB1W/=01T2rdGR11111 (rd)ALU11111DBDR1執(zhí)行周期T0DRALU1T1+11111111T2ALUGR1111111ALU PC1所有指令：PCAB = M0·T0W/=0 = M0·T0+M1·T1·取數DBIR = M0·T1PC+1 = M0 ·T2rs1GR = M1 ·T0(rs1)ALU = M1 ·T0+ = M1 ·T0·取數 +M2·T1·(加+傳送+取數+轉移)ALUAR =M1 ·T1 ·取數AR

10、AB =M1·T1 ·取數rdGR =M1 ·T2·(加法+與+或+左移+右移)(rd)ALU = M1 ·T2·(加法+與+或+左移+右移)DBDR = M1 ·T2·取數DRALU = M2 ·T0·取數 = M2·T1·與 = M2·T1·或 = M2·T1·左移 = M2·T1·右移ALUGR = M2·T2·(加法+與+或+左移+右移+數據傳送+取數)ALU PC = M2·T

11、2·轉移3、層次結構控制單元：t0 q18 q0 m0t1 控制單元 m1t2 d7 d0 m2邏輯圖：i7 i0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 3-8譯碼器 S A2 A1 A0t0 q18 q0 m0t1 控制單元 m1t2 d7 d0 m2 S A2 A1 A0T0T1T2M0M1M2 Q18 Q0 三、VHDL程序-3-8譯碼器library ieee;use ieee.std_logic_1164.all;entity decoder38 is port( S:in std_logic; A:in std_logic_vector(2 downto 0);

12、 Y:out std_logic_vector(7 downto 0);end decoder38;architecture behave of decoder38 isbegin process(S) begin if S='1' then Y(0)<=(not A(2) and (not A(1) and (not A(0); Y(1)<=(not A(2) and (not A(1) and A(0); Y(2)<=(not A(2) and A(1) and (not A(0); Y(3)<=(not A(2) and A(1) and A(0)

13、; Y(4)<=A(2) and (not A(1) and (not A(0); Y(5)<=A(2) and (not A(1) and A(0); Y(6)<=A(2) and A(1) and (not A(0); Y(7)<=A(2) and A(1) and A(0); else Y<="00000000" end if; end process;end behave;-控制單元-3-8譯碼器library ieee;use ieee.std_logic_1164.all;entity CU is port( m:in std_lo

14、gic_vector(2 downto 0); t:in std_logic_vector(2 downto 0); d:in std_logic_vector(7 downto 0); q:out std_logic_vector(18 downto 0);end CU;architecture behave of CU issignal iq:std_logic_vector(7 downto 0);begin iq(0)<=not d(7) and not d(6) and not d(5) and not d(4) and not d(3) and not d(2) and no

15、t d(1) and d(0); iq(1)<=not d(7) and not d(6) and not d(5) and not d(4) and not d(3) and not d(2) and d(1) and not d(0); iq(2)<=not d(7) and not d(6) and not d(5) and not d(4) and not d(3) and d(2) and not d(1) and not d(0); iq(3)<=not d(7) and not d(6) and not d(5) and not d(4) and d(3) an

16、d not d(2) and not d(1) and not d(0); iq(4)<=not d(7) and not d(6) and not d(5) and d(4) and not d(3) and not d(2) and not d(1) and not d(0); iq(5)<=not d(7) and not d(6) and d(5) and not d(4) and not d(3) and not d(2) and not d(1) and not d(0); iq(6)<=not d(7) and d(6) and not d(5) and not

17、 d(4) and not d(3) and not d(2) and not d(1) and not d(0); iq(7)<=d(7) and not d(6) and not d(5) and not d(4) and not d(3) and not d(2) and not d(1) and not d(0); q(0)<=not m(2) and not m(1) and m(0) and not t(2) and not t(1) and t(0); q(1)<=(not m(2) and not m(1) and m(0) and not t(2) and

18、not t(1) and t(0) or (not m(2) and m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(6); q(2)<=not m(2) and not m(1) and m(0) and not t(2) and t(1) and not t(0); q(3)<=not m(2) and not m(1) and m(0) and t(2) and not t(1) and not t(0); q(4)<=not m(2) and m(1) and not m(0) and not t

19、(2) and not t(1) and t(0); q(5)<=not m(2) and m(1) and not m(0) and not t(2) and not t(1) and t(0); q(6)<=(not m(2) and m(1) and not m(0) and not t(2) and not t(1) and t(0) and iq(6) or (m(2) and not m(1) and not m(0) and not t(2) and t(1) and not t(0) and (iq(0) or iq(5) or iq(6) or iq(7); q(

20、7)<=not m(2) and m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(6); q(8)<=not m(2) and m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(6);q(9)<=not m(2) and m(1) and not m(0) and t(2) and not t(1) and not t(0) and (iq(0) or iq(1) or iq(2) or iq(3) or iq(4);q(10)<

21、=not m(2) and m(1) and not m(0) and t(2) and not t(1) and not t(0) and (iq(0) or iq(1) or iq(2) or iq(3) or iq(4); q(11)<=not m(2) and m(1) and not m(0) and t(2) and not t(1) and not t(0) and iq(6); q(12)<=m(2) and not m(1) and not m(0) and not t(2) and not t(1) and t(0) and iq(6); q(13)<=m

22、(2) and not m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(1); q(14)<=m(2) and not m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(2); q(15)<=m(2) and not m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(3); q(16)<=m(2) and not m(1) and not m(0) and not t

23、(2) and t(1) and not t(0) and iq(4); q(17)<=m(2) and not m(1) and not m(0) and t(2) and not t(1) and not t(0) and (iq(0) or iq(1) or iq(2) or iq(3) or iq(4) or iq(5) or iq(6); q(18)<=m(2) and not m(1) and not m(0) and t(2) and not t(1) and not t(0) and iq(7);end behave;-層次結構控制單元library ieee;us

24、e ieee.std_logic_1164.all;entity HCU is port( S:in std_logic; A:in std_logic_vector(2 downto 0); M:in std_logic_vector(2 downto 0); T:in std_logic_vector(2 downto 0); Q:out std_logic_vector(18 downto 0);end HCU;architecture struct of HCU issignal i:std_logic_vector(7 downto 0);component decoder38 po

25、rt( S:in std_logic; A:in std_logic_vector(2 downto 0); Y:out std_logic_vector(7 downto 0);end component;component CU port( m:in std_logic_vector(2 downto 0); t:in std_logic_vector(2 downto 0); d:in std_logic_vector(7 downto 0); q:out std_logic_vector(18 downto 0);end component;begin G1:decoder38 por

26、t map (S=>S,A=>A,Y=>i); G2:CU port map (d=>i,t=>T,m=>M,q=>Q);end struct;四、仿真設計3-8譯碼器仿真設計：設計數據，輸出3-8譯碼器的譯碼后的8種編碼。S111111110A000001010011100101110111101Y000000010000001000000100000010000001000000100000010000001000000000000000控制成員仿真設計：設計仿真數據使每一個微操作都可以有效輸出：m001001001010100t001010100

27、001010d0001000000100000100000000100000000000001q00000000000000000110000000000000000100000000000000000100000000000000011100000000000000001000000m010010010100100t010100100001010d0100000000001000010000000100000000000010q00000000001100000100000000011000000000000000010000000000000000010000000000000000010

28、000000000000m100100100100100t010010010100100d0000010000001000000100000000001010000000q00001000000000000000001000000000000000001000000000000000001000000000000000001000000000000000000層次控制單元仿真設計：設計數據依次輸出8條指令的微操作：例如：若要輸出加法指令需要的所有微操作，則需設置數據如下：S1111A000000000000M001001001010T001010100001Q0000000000000000011000000000000000010000000000000000010000000000000000110000S111A000000000M010100100T100010100Q000000001100000000000000000000010000000100000000000000000由于每條指令都有取指令這個微指令，因此在下面的測試數據中將不再測試取指令的微操作。與：S1111A001001001001M010010100100T001100