設(shè)計於深次微米CMOS制程之功率感知高速類比數(shù)位轉(zhuǎn)換積

1、設(shè)計於深次微米CMOS製程之功率感知高速類比數(shù)位轉(zhuǎn)換積體電路(Power-Aware High-Speed ADC in Deep Submicron CMOS)文化大學(xué)電機系2011年先進電機電子科技研討會Outline Motivation High-speed ADC IC design example Digitally-assisted algorithm and architecture Circuit implementation Experimental results Summary2High-Speed ADC Applications Ref 13Power-Aware

2、High-Speed ADC Trends Power / EnergyHigher resolution requires more energy to achieve.Speed / BandwidthResolution and speed are trade-offs.BottleneckSAR architecture saves power and chip area, but speed is limited by its conversion algorithm.Pipelined architecture achieves high speed by concurrent o

3、perations, but OPAs consume considerable power.Digitally assisted ADCsDigitally assisted algorithm alleviates analog circuit requirement; therefore, it takes advantages of advanced processes to trade little digital power to gain the benefits from analog part.4High-Speed ADC Energy vs. SNDREnergy is

4、proportional to resolution (SNDR).FOM (Power / (Sample rate * 2ENOB) is an indicator to compare different ADC designs.State-of-the-art ADC designs approach 10fJ/c.s. Current world record is 4fJ/c.s. Ref 25High-Speed ADC Bandwidth vs. SNDRBandwidth is inverse proportional to resolution (SNDR).State-o

5、f-the-art high-speed high-resolution ADCs are limited by clock jitter around 0.1psrms. Ref 26Experiment 1 - Low-Power High-Speed Two-Step ADCRearrange the timing of two-channel MDACs and apply a self-timing technique to alleviate comparator comparison time and charge injection disturbanceSlightly in

6、creases CADC accuracy to ease OPA signal swing design Ref 3Technology0.13mResolution6-bitActive area0.16mm2Supply voltage1.2VSample rate1-GS/sSFDR (FinNq)40.7dBSNR (FinNq)33.8dBSNDR (FinNq)33.7dBPower49mWFoM1.24pJ/c.s.7Relieve MSB accuracy requirement by the sub-range concept with overlappingReduce

7、total input capacitance by using the double-unit-sized coupling-capacitor Ref 4Experiment 2 - Low-Power High-Speed Sub-range SAR ADCTechnology0.13mResolution12-bitActive area0.096mm2Supply voltage1.2VSample rate10MS/sSFDR (FinNq)69.8dBSNR (FinNq)61.2dBSNDR (FinNq)59.7dBPower3mWFoM0.38pJ/c.s.8Attain

8、high conversion speed by adopting non-constant-radix switching methodCompared to conventional non-binary designs, its DAC implementation is simpler.Experiment 3 - Low-Power High-Speed SAR ADCTechnology90nmResolution10-bitChip area1.029mm2Supply voltage1.0VSample rate40MS/sSFDR (FinNq)61.9dBSNDR (Fin

9、Nq)54.1dBPower1.34mWFoM81.1fJ/c.s.9Achieve high speed with a low-gain OPA by using digitally-assisted architecture, thus the OPAs have excellent power efficiencyA simple gain-error self calibration method without external precise references requires only 168 calibration clock cycles.Ref 5Experiment

10、4 - Low-Power High-Speed Pipelined ADCTechnology90nmResolution10-bitActive area0.21mm2Supply voltage1.2VSample rate320MS/sSFDR (FinNq)66.7dBSNDR (FinNq)51.2dBPower42mWFoM0.44pJ/c.s.10Digitally-Assisted High-Speed ADC Example (Experiment 4) Digitally assisted architecture is future trend to achieve e

11、xcellent power efficiency.10b, several hundreds MS/s Pipeline ADCs are widely used in wireless and cloud computing systems but suffer from OPA design in deep submicron CMOS processes.Decreased OPA DC gainSmaller signal swing11Pipeline ADC Accuracy OPA gainLess Ro of MOSFET in advanced technologiesRe

12、duced gain from each stage of OPAMore gain stages introduce poles and decrease bandwidth.For 10b accuracy, the 1st stage MDAC requires 66dB OPA DC gain.Capacitor mismatchRaw matching can attain 10b accuracy, not an issue!12Closed-Loop Gain Error 13For finite A, closed-loop gain ACL is smaller than i

13、deal gain, 1/b.Gain error can be compensated by adjusting b. Due to finite A, closed-loop gain is less than ideal value of 4.b adjustment is proposed to correct MDAC gain error. 14MDAC Gain ErrorProposed MDAC with a Calibration Capacitor A calibration capacitor, Ccal, is added as a positive feedback

14、 to adjust b.Closed-loop gain can achieve 10b accuracy with low DC gain A of 30dB.15Self-Calibrated Algorithm (1) Self-calibrated procedure starts with the last stage MDAC.After MDAC is calibrated, it is treated as “ideal MDAC.Ideal MDACs subtract 3Vref/8 and then multiply 4.Under-Calibration MDAC s

15、amples Vref/8 and then multiplies 4.16Self-Calibrated Algorithm (2) Gain Error Output is Vref/2 when no gain errorUsing successive approximation method with iterations, the closed-loop gain reaches 4 with 10b accuracy.17Proposed ADC Architecture On-chip foreground analog self-calibrated techniqueGai

16、n errors of first three stages are calibrated18Calibration Step 128 calibration stepsEach step affects 0.14 % of MDAC gain (4) with OPA gain of 40dB19Calibration Range Ccal in this work can calibrate OPA with a minimum DC gain of 30dB20OPA Use small L to increase bandwidth without considering gainCa

17、libration mode has more compensation capacitanceSimulation results: DC gain 40dB, closed-loop BW 1.36GHz 21Chip Micrograph 2 active area in 90 nm low-power CMOS22Measured DNL Before calibration: +1.7 / -1.0 LSB Before calibrationAfter calibration23Measured INL Before calibrationAfter calibration24Me

18、asured Dynamic Performance At low FinAt Nyquist FinERBW 160MHz25Measured FFT SNDR 52.8dB and SFDR 57.8dB when Fs = 320MHz and Fin = 128MHz26Measured Performance Summary JSSC09 7ISSCC07 8This WorkTechnology (nm)9013090Calibration MethodForegroundForeground/BackgroundForegroundSample Rate (MS/s) 50020

19、5320Resolution (bit)101010DNL/INL (LSB)0.4/1.00.15/0.60.7/0.9Peak SNDR (dB)55.85654.2SNDR (dB) at Fs/2535651.2SFDR (dB)-73.566.7Power (mW)5592.542FoM (fJ/c.-s.)301881442Active Area (mm2)0.490.520.21NoteCalibration circuit is off-chipInput buffer power is included27Summary A simple self-calibrated al

20、gorithm is proposed to correct gain error resulting from low gain OPA in deep submicron CMOS.The self-calibrated process does not require a precise external reference and can be done within only 168 clock cycles.2 in 90nm CMOS including calibration circuitThe prototype ADC achieves 320MS/s conversio

21、n rate, 8.7 ENOB and only consumes 42mW. Nice power efficiency is obtained.Power efficiency is the key to high-speed ADC IC designs.28Reference 2 B. Murmann, ADC Performance Survey 1997-2010, Online. Available:mm CMOS, IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3051-3059, Nov. 2009.4 H. Chen

22、 et al., “A 3mW 12b 10MS/s Sub-Range SAR ADC in IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, Taipei, Taiwan, pp. 153-156, Nov. 2009.5 H. Chen et al., “A 10b 320MS/s Self-Calibrated Pipeline ADC in IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, Peking, China, pp. 173-176, Nov. 2

23、010.6 B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High-Resolution Comparators, IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992.7 A. Verma and B. Razavi, A 10b 500MHz 55mW CMOS ADC, IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3039-3050, Nov. 2009.mm C

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