cadence ic設(shè)計(jì)全版圖其他ds2001roadshow

1、Cadence Design Systems, Inc. Cadences Solution for High-Speed Design 2 confidential Agenda What is High-Speed Design? Ideal High-Speed Design Process Introduction to SPECCTRAQuest Power Integrity SPECCTRAQuest Demonstration 3 confidential R The Day of “High-Speed” Has Come “Pc-board designers, meanw

2、hile, were retooling in 1999 for high-speed design. Signal integrity, once confined to high-end boards, has become everybodys problem” Richard Goering, commenting on why the PCB layout market grew 20% while the IC layout market shrunk 30%, in EETimes 4/10/2000 page 70 4 confidential Welcome Networki

3、ng! Hammerhead Networks R 5 confidential Agenda What is High-Speed Design? Ideal High-Speed Design Process SPECCTRAQuest Demonstration Introduction to SPECCTRAQuest Power Integrity NOW 6 confidential What is “High-Speed” ? Over 50 MHz is “High-Speed” “High-Speed” isnt related to frequency, its a fun

4、ction of rise times A net is “High-Speed” when its round-trip delay is greater than twice its edge-speed A signal is “High-Speed” when it is faster than anything youve designed before “High-Speed” occurs when“High-Speed” occurs when skin effectskin effect and dielectric and dielectric loss effects b

5、ecome importantloss effects become important Huh? 7 confidential Question: Which is a “High-Speed” Problem? 8 confidential Answer: They BOTH Are ! 9 confidential Definition of High-Speed A net can be considered High-Speed when you have to do something other than simply connect it. 10 confidential Hi

6、gh-Speed Design Involves 2 Things Nets that are understood, and must be constrained Nets that must be analyzed to be understood, and then constrained 11 confidential Nets that are understood, and must be constrained Nets that must be analyzed to be understood, and then constrained SDRAM DIMM Layout

7、MODELS Datasheets Front-side Bus Simulation 12 confidential Most Tools Force You to Choose Great Simulator! AnalyzeConstrain Great Layout System! Hmm. 13 confidential But for High-Speed You Need BOTH All in ONE integrated & interactive environment ! Analyze & Constrain Lets Go! 14 confidential 15 co

8、nfidential SPECCTRAQuest: Integrated Constraint & Analysis Model Development & Verification Topology Entry & Floorplanning Constraint Driven Layout Analyze Constrain SPECCTRAQuest helps you manage the process of High-Speed PCB development through both Simulation Analysis & Constraint-Driven Layout t

9、asks A Complete Solution! Pre-Route Soln-Space Analysis Post Route Analysis Verification Verification 16 confidential Expanding Existing Process Physical Model Creation Outline/ Floorplan/ Room Def/ Schematic Model Creation Schematic Creation SCHEMATICLAYOUT To Final Verification netlist SI Clean Ro

10、ute constraints Back- Annotate Re-use Topology Files Topology Files Topology Files Derive Constraints Electrical Model Creation HIGH-SPEED yes no Post-Route Analysis rules/ criticals/ placement / ACs OK? “IP” Library PCB Routing 17 confidential Agenda What is High-Speed Design? Ideal High-Speed Desi

11、gn Process SPECCTRAQuest Demonstration Introduction to SPECCTRAQuest Power Integrity NOW 18 confidential Ideal High-Speed Design Flow Model Development & Verification Topology Entry & Floorplanning Constraint Driven Layout Analyze Constrain Development Process Flow Pre-Route Soln-Space Analysis Post

12、 Route Analysis Verification Verification Model Development & Verification 19 confidential Need Flexible Device Modeling Language (DML) Todays models come in many styles and formats Cadence DML can model all formats AND advanced behaviors (for example, Merced / Itanium) Quad Models Version 2.1 Versi

13、on 3.2 IBIS Package, Transmission Line, Connector, Cable Models SPICE Models EBD Models Cadence DML cant do “M” element today 20 confidential Ideal High-Speed Design Flow Model Development & Verification Topology Entry & Floorplanning Constraint Driven Layout Analyze Constrain Development Process Fl

14、ow Pre-Route Soln-Space Analysis Post Route Analysis Verification Verification Pre-Route Soln-Space Analysis 21 confidential Pre-Route Solution Space Analysis Exhaustive “pre-layout” analysis of manufacturing and design variances Used to define topologies, routing rules and termination strategies Cr

15、osstalk and data pattern dependencies may be taken into consideration Swept-parameter analysis is used extensively to cover all combinations of conditions Need flexibility to define any kind of simulation and any kind of measurement criteria 22 confidential Output of pre-layout process is an electro

16、nic constraint file that can be used to guide the layout process Analyze Topology Templates Derive and Save “Solution Space” Constrain 23 confidential Ideal High-Speed Design Flow Model Development & Verification Topology Entry & Floorplanning Constraint Driven Layout Analyze Constrain Development P

17、rocess Flow Pre-Route Soln-Space Analysis Post Route Analysis Verification Verification Topology Entry & Floorplanning 24 confidential High-Speed PCB Design Now Requires Both Electronic Inputs to Floorplanning & Routing Topology Files Final Netlist ELECTRICAL LOGICAL PCB Routing PHYSICAL Topology Fi

18、les Final Netlist ELECTRICAL LOGICAL PCB Routing PCB Routing PHYSICAL 25 confidential Topology Entry and Floorplanning Design rules derived from solution space analysis guide the placement process Constraint Manager spreadsheets plays a key role in guiding / evaluating component placement Margin col

19、umns show difference between constraint and design value Fast feedback Color-coded status Topology Templates 26 confidential Ideal High-Speed Design Flow Model Development & Verification Topology Entry & Floorplanning Constraint Driven Layout Analyze Constrain Development Process Flow Pre-Route Soln

20、-Space Analysis Post Route Analysis Verification Verification Constraint Driven Layout 27 confidential ConceptHDL Capture SPECCTRAQuest Exploration SPECCTRAQuest Floorplanning Allegro/APD Layout Constraint Manager CaptureExplorationFloorplanningLayout GUIGUIGUIGUI ConstraintsConstraintsConstraintsCo

21、nstraints ? ? ePlanner/QUAD SPICE HyperLynx ViewDraw ICX Design Board Station PADS VeriBest Architect ePlanner Constraint Management Today 28 confidential PSD 14.0 Constraint Manager Common, powerful environment for constraint entry / editing / management and verification Single mechanism for managi

22、ng constraints throughout the design process 29 confidential Constraint Manager Key Features Spreadsheet-based graphical interface No cryptic formats or cumbersome updating Provides unsurpassed Integration across the entire design flow Consistent Front to Back solution No messy translations with sta

23、tic constraint data Directly integrated with schematic and PCB databases Analysis engines can update spreadsheet data interactively 30 confidential Constraint Manager Hierarchy Allows constraints to be managed hierarchically Groups of rules are maintained as Electrical Constraint Sets (ECSets) Provi

24、des single point for updating rules or assigning to nets ECSets can be applied to groups of nets (buses) with individual overrides 31 confidential Constraint Manager Systems Support for system level constraints Constraints can span PCB boundaries Chipset TerminationRIMM 32 confidential Topology Temp

25、lates Constraint Driven Layout Guides: Floorplanning Hand Layout Auto-Route 33 confidential Constraint Driven Layout Design rule violations during interactive routing are identified in real-time Autorouter follows design rules - powerful integration with SPECCTRA! Because solution space analysis has

26、 defined a set of conditions under which the nets are known to work, chance of first-pass success is high. Nets can be ripped up and rerouted, as long as they still adhere to the design rules 34 confidential Ideal High-Speed Design Flow Model Development & Verification Topology Entry & Floorplanning

27、 Constraint Driven Layout Analyze Constrain Development Process Flow Pre-Route Soln-Space Analysis Post Route Analysis Verification Verification Post Route Analysis VerificationVerification 35 confidential Agenda What is High-Speed Design? Ideal High-Speed Design Process Introduction to SPECCTRAQues

28、t Power Integrity SPECCTRAQuest Demonstration NOW Cadence Design Systems, Inc. SPECCTRAQuest Power Integrity Module The Future of Power Delivery System Design 37 confidential SPECCTRAQuest Power Integrity Innovative technology developed and proven by Sun Microsystems, now commercialized by Cadence D

29、esign Systems, Inc. to address Power Delivery issues in high-speed PCB System Designs. A design tool / methodology used to design and optimize the frequency-dependent characteristics of Power Delivery Systems in high-speed system designs An integrated solution to allow many quick iterations of “chan

30、ge-simulate-analyze” 38 confidential Power Delivery Requirements Trend Power dissipation and longer battery life fueling decreasing chip power supply voltages Maximum allowable supply ripple decreases accordingly SoC, SiP fueling trend towards devices with large number of devices The instantaneous s

31、witching current required is enormous The maximum acceptable power supply ripple voltage determines the target impedance which must be maintained across the PCB Maximum supply impedance must be less than 0.002 Ohms 39 confidential Power Delivery System Design Challenges Power supply droop Alters sys

32、tem timing and can cause Setup failures Can cause sampling errors that results in a system crash Unreliable power delivery system design can cause increased common-mode EMI preventing product shipment due to compliance problems Power delivery system impedance is frequency-dependent Must be controlle

33、d for all frequency range of all transient currents Increases Development Costs and Time to Market is LOST! 40 confidential Power Delivery System Design - How it is done today Standalone analysis tools Design data translation is left up to the user Changes to the design resulting from simulation is

34、manual Use Time Domain simulation Power delivery system impedance is frequency-dependent! With only time domain simulation, it is like searching for needle in a haystack Over design - add more de-coupling capacitors than necessary Expensive solution that may not work 41 confidential The Cadence appr

35、oach Allow users to determine the needs of the power delivery system Target impedance Decoupling capacitor requirements Provide frequency domain analysis to find problem areas Provide an integrated PCB design editor to optimize capacitor placement Develop reliable power delivery system while shorten

36、ing design cycle time 42 confidential SPECCTRAQuest Power Integrity - Software Components Frequency-domain analysis engine Integrated PCB editor that includes Decoupling capacitor placement environment Impedance requirements calculator Decoupling requirements wizard High speed capacitor library / li

37、brary editor 43 confidential Isolating Decoupling Problem Areas 44 confidential Device Placement Decoupling Capacitors Capacitors can be selected from the decoupling “menu” and placed into the design The effective decoupling radius is automatically displayed as the capacitor is positioned Designers

38、continue to adjust capacitor selection & placement until performance of the PDS is acceptable Allows many “change-simulate-analyze” cycles in a short time 45 confidential Release Available with PSD release version 14.1 Scheduled for late Q2, 2001 First release available on Sun Solaris (7 / 8) only O

39、ther platforms to follow with next major release 46 confidential SPECCTRAQuest Power Integrity - Summary Innovative technology developed and proven by Sun Microsystems, commercialized by Cadence Combined toolset and methodology for the design and analysis of high performance power delivery systems O

40、ffered as an option to SPECCTRAQuest, integrated with Allegro Part of Cadences complete family of Signal Integrity / Power Delivery / EMI solutions Shortens Development Cycle and Time to Market! 47 confidential Agenda What is High-Speed Design? Ideal High-Speed Design Process Introduction to SPECCTRAQuest Power Integrity SPECCTRAQu