數(shù)字邏輯設(shè)計(jì) - 基礎(chǔ)理論知識(shí)

數(shù)字系統(tǒng)設(shè)計(jì)Digital

System

Design?

Digital

System

Design32015

ZDMC

–

Lec.

#1課程簡(jiǎn)介

參考書

閻石,

數(shù)字電子技術(shù)基礎(chǔ),第5版,

高等教育出版社,

2006.

R

J.

Tocci

et

al.,

Digital

Systems

Principles

and

Applications,

Tenth

Edition,

2006.

R.H.Katz,

G.Borriello,

Contemporary

Logic

Design,

second

edition,電子工業(yè)出版社,

2005.

M.M.Mano,

Michael

D.Ciletti,

Digital

Design,

Fourth

Edition,

數(shù)字設(shè)計(jì)(第四版),

電子工業(yè)出版社,

2008.

–

/mano

補(bǔ)充材料，見網(wǎng)頁(yè)

/liupeng/教學(xué)工作

數(shù)字系統(tǒng)設(shè)計(jì)考核

平時(shí)30%(作業(yè),

測(cè)驗(yàn),

上課,

期中考試)

期末考試70%答疑

信電樓307房間/周五下午3:00-4:30?

Digital

System

Design42015

ZDMC

–

Lec.

#1課程結(jié)構(gòu)

基礎(chǔ)理論知識(shí)(必備)

數(shù)字系統(tǒng)和編碼、布爾代數(shù)門電路數(shù)字電路分析與設(shè)計(jì)

組合電路

時(shí)序電路控制器和微碼多節(jié)拍微處理器設(shè)計(jì)測(cè)試和驗(yàn)證脈沖電路?

Digital

System

Design52015

ZDMC

–

Lec.

#1數(shù)字系統(tǒng)-設(shè)計(jì)抽象級(jí)別(Design

Abstraction

Levels）n+n+SGD+

GATECIRCUIT

DEVICEMODULESYSTEM?

Digital

System

Design62015

ZDMC

–

Lec.

#1設(shè)計(jì)準(zhǔn)則

（Design

Metrics）

如何評(píng)價(jià)數(shù)字電路的性能

(Figure

of

Merit)

成本Cost可靠性Reliability可擴(kuò)展性Scalability速度Speed

(delay,

operating

frequency)功耗Power

dissipation能耗Energy

to

perform

a

function?

Digital

System

Design72015

ZDMC

–

Lec.

#1

同步數(shù)字系統(tǒng)

(Digital

Systems)同步數(shù)字硬件系統(tǒng)Synchronous

Digital

Hardware

SystemsA

series

of

numbers

is

used

to

represent

the

waveform,

rather

than

a

voltage

or

current,

as

in

analog

systems.

同步（Synchronous）:

“Clocked”

-

all

changes

in

the

system

are

controlled

by

a

global

clock

and

happen

at

the

same

time

(not

asynchronous)

數(shù)字（Digital）:

All

inputs/outputs

and

internal

values

(signals)

take

on

discrete

values

(not

analog).

Example

digital

representation:

acoustic

waveform?

Digital

System

Design82015

ZDMC

–

Lec.

#1數(shù)字系統(tǒng)例子-1

數(shù)字計(jì)算機(jī)-

最小化成本

最大化能效

計(jì)算器?

Digital

System

Design92015

ZDMC

–

Lec.

#1數(shù)字系統(tǒng)例子-2

數(shù)字手表

最小化功耗.

電池可維持?jǐn)?shù)年

可穿戴設(shè)備?

Digital

System

Design數(shù)字系統(tǒng)設(shè)計(jì)例子-3

The

TROJAN

PROOF

CHIP102015

ZDMC

–

Lec.

#1?

Digital

System

Design112015

ZDMC

–

Lec.

#1設(shè)計(jì)折中

設(shè)計(jì)規(guī)范-

功能性描述.

–性能（速度）

–成本（復(fù)雜性）

–功耗（能量消耗）

作為設(shè)計(jì)人員必須在約束條件下實(shí)現(xiàn)預(yù)期的

功能。?

Digital

System

Design122015

ZDMC

–

Lec.

#1設(shè)計(jì)表達(dá)?

Digital

System

Design132015

ZDMC

–

Lec.

#1

AnalogBasebandDigital

Baseband

(DSP

+

MCU)

PowerManagement

SmallSignal

RFPower

RFCellPhoneSystem-on-a-Chip

design

:

integrates

processors,External

IO?

Digital

System

Design14Blue

Gene/QCompute

chip

360

mm2Cu-45

technology

(SOI)

~

1.47

B

transistors16

user

+

1

service

processors

plus

1

redundant

processor

all

processors

are

symmetric

each

4-way

multi-threaded

64

bits

PowerISA?

1.6

GHz

L1

I/D

cache

=

16kB/16kB

L1

prefetch

engines

each

processor

has

Quad

FPU

(4-wide

double

precision,

SIMD)

peak

performance

204.8

GFLOPS@55WCentral

shared

L2

cache:

32

MB

eDRAM

multiversioned

cache

will

support

transactional

memory,

speculative

execution.

supports

atomic

opsDual

memory

controller

16

GB

external

DDR3

memory

1.33

Gb/s

2

*

16

byte-wide

interface

(+ECC)Chip-to-chip

networking

Router

logic

integrated

into

BQC

chip.

PCIe

Gen2

interface2015

ZDMC

–

Lec.

#1memory

and

networking

logic

into

a

single

chip

?

Digital

System

Design162015

ZDMC

–

Lec.

#1目標(biāo)

數(shù)字電路設(shè)計(jì)的基礎(chǔ)理論

數(shù)字系統(tǒng)分析方法

數(shù)字系統(tǒng)設(shè)計(jì)方法

數(shù)字系統(tǒng)實(shí)現(xiàn)和測(cè)試方法

數(shù)字系統(tǒng)設(shè)計(jì)和解決問題的基本技能

電路圖

硬件描述語(yǔ)言

語(yǔ)言描述問題?

Digital

System

Design172015

ZDMC

–

Lec.

#1邏輯代數(shù)基礎(chǔ)（復(fù)習(xí)）?

Digital

System

Design182015

ZDMC

–

Lec.

#1邏輯代數(shù)概述

基本概念-布爾代數(shù)

邏輯：

事物的因果關(guān)系

邏輯運(yùn)算的數(shù)學(xué)基礎(chǔ)：

邏輯代數(shù)

在二值邏輯中的變量取值：

0/1

用簡(jiǎn)單(0/1)代數(shù)描述復(fù)雜性事物?

Digital

System

Design192015

ZDMC

–

Lec.

#1邏輯代數(shù)中的三種基本運(yùn)算或（OR）非（NOT與（AND）

）1）以A=1表示開關(guān)A合上，A=0表示開關(guān)A斷開；2）以Y=1表示燈亮，Y=0表示燈不亮；三種電路的因果關(guān)系不同：?

Digital

System

Design202015

ZDMC

–

Lec.

#1

與

-AND

條件同時(shí)具備，結(jié)果發(fā)生

Y=

A

AND

B

=

A&B

=

A·B

=

AB

真值表/truth

table圖形符號(hào)A0011B0101Y0001國(guó)標(biāo)國(guó)際?

Digital

System

Design212015

ZDMC

–

Lec.

#1

或-OR

條件之一具備，結(jié)果發(fā)生

Y=

A

OR

B

=

A+B

真值表圖形符號(hào)A0011B0101Y0111?

Digital

System

Design222015

ZDMC

–

Lec.

#1

真值表圖形符號(hào)非-NOT(反相器)

條件不具備，結(jié)果發(fā)生

Y

A

NOT

AA01Y10?

Digital

System

Design232015

ZDMC

–

Lec.

#1幾種常用的復(fù)合邏輯運(yùn)算1

與非-NAND

或非-NOR與或非AND-NOR?

Digital

System

Design242015

ZDMC

–

Lec.

#1幾種常用的復(fù)合邏輯運(yùn)算2

異或-EXCLUSIVE

OR

Y=

A

BA0011B0101Y0110?

Digital

System

Design252015

ZDMC

–

Lec.

#1幾種常用的復(fù)合邏輯運(yùn)算3

同或-EXCLUSIVE

NOR

/符合

Y=

A

⊙BA0011B

0

1

0

1Y1001?

Digital

System

Design262015

ZDMC

–

Lec.

#1邏輯代數(shù)的基本公式和常用公式

基本公式

運(yùn)算規(guī)則：交換律、結(jié)合律、分配律、重疊律、互補(bǔ)

律、反演律、還原律、逆；

常用公式

符號(hào)的優(yōu)先級(jí)：1）括號(hào)，2）非，3）與，4）或。?

Digital

System

Design272015

ZDMC

–

Lec.

#1基本公式

根據(jù)與、或、非的定義，得布爾恒等式序號(hào)公式序號(hào)公式101112131415161718

1′

=

0;

0′=

1

1

+

A=

1

0

+A=A

A+A=A

A

+

A′

=

1

A

+B

=

B

+

AA

+

(B

+C)

=

(A

+

B)

+

C

A

+

B

C

=

(A

+B)(A

+C)

(A+

B)

′

=

A′B′123456789

0

A

=

0

1

A

=

A

AA=A

A

A′=

0

AB=BA

A

(B

C)

=

(A

B)

CA

(B

+C)

=

A

B

+

A

C

(A

B)

′

=

A′

+

B′

(A

′)

′

=

A證明方法：推演

真值表?

Digital

System

Design282015

ZDMC

–

Lec.

#1公式（17）的證明（公式推演法）：A+BC=(A+B)(A+C)

右

(A

B)(A

C)

A

AB

AC