存儲(chǔ)器輸入輸出訪問(wèn)中英文對(duì)照外文翻譯文獻(xiàn)

PAGE17中英文資料對(duì)照外文翻譯原文：Input/OutputAccessingInthisarticle,wewilllookatthethreebasicmethodsofI/Oaccessing－programmedI/O,interrupt-drivenI/O,anddirectmemoryaccess(DMA).ThekeyissuethatdistinguishesthesethreemethodsishowdeeplytheprocessorisinvolvedinI/Ooperations.Thediscussionemphasizesinterrupt-drivenI/O,becauseitisbasedontheconceptofinterrupthandling,whichisageneralproblemthatgoesbeyondInput/Outputoperations.Thestudyofinterrupthandlingalsoaidsinunderstandingthegeneralconceptofexceptionprocessing,whichisanimportantissuenotonlyforI/O,butalsoforinterfacingacomputerwithothersystemcontrolfunctions.AddressingI/ORegistersInput/OutputdevicescommunicatewithaprocessorthroughInput/Outputports.Throughtheinputports,sprocessorreceivesdatafromtheI/Odevices.Throughtheoutputports,aprocessorsendsdatatotheI/Odevices.EachI/Oportconsistsofasmallsetofregisters,suchasdatabufferregisters(theinputbufferand/ortheoutputbuffer),thestatusregister,andthecontrolregister.Theprocessormusthavesomemeanstoaddresstheseregisterswhilecommunicatingwiththem.TherearetwocommonmethodsofaddressingI/Oregister－memory-mappedI/OanddirectI/O.1. Memory-MappedI/OMemory-mappedI/OmapstheI/Oregistersandmainmemoryintoaunifiedaddressspaceinthecomputersystem.I/Oregisterssharethesameaddressspacewithmainmemory,butaremappedtoaspecificsectionthatisreservedjustforI/O.Thus,theI/Oregistercanbeaddressedinordinarymemoryreferenceinstructionsasiftheyarepartofthemainmemorylocations.TherearenospeciallydesignedI/Oinstructionsintheinstructionsetofthesystem.AnyinstructionthatreferencesalocationinthisareaisanI/Oinstruction.AnyinstructionthatcanspecifyamemoryaddressiscapableofperformingI/Ooperations.TheMotorolaMC68000isanexampleofacomputersystemthatusesthisaddressingmethod.2. DirectI/OThemethodofaddressingI/OregistersdirectlywithoutsharingtheaddressspacewiththemainmemoryiscalleddirectI/OorI/O-mappedI/O.Inotherwords,I/Oregistersarenotmappedtothesameaddressspacewiththemainmemory.EachI/Oregisterhasanindependentaddressspace.Asaresult,instructionsthatreferencethemainmemoryspacecannotbeusedforInput/Output.Intheinstructionsetofthecomputersystem,specialI/OinstructionsmustbedesignedforI/Ooperations.IntheseI/Oinstructions,distinctI.D.numbersmustbeusedtoaddressdifferentI/Ocommunicationchannels(i.e.,I/Oports).Theyarecalledportnumbers.TheI/OregistersofanI/OportareconnectedtothesystemI/Obus,throughwhichtheprocessorcanreferencetheI/Oregistersdirectlytosend/receivedatato/fromanI/Odevice.AnI/Oportnumberisnotfromthesameaddressspaceasmainmemory.ThePentiumisanexampleofacomputersystemthatusesthedirectI/Oaddressingmethod.Ithasa64GBmemoryaddressspace(32addressbits)and,atthesametime,a64KBI/Oaddressspace(16bitsI/Oaddress/portnumber).Wecancomparememory-mappedI/OandthedirectI/OandthedirectI/Oasfollows:● Memory-mappedI/OusesordinarymemoryreferenceinstructionstoaccessI/O,soitprovidesflexibilityforI/OprogrammingandsimplifiesI/Osoftware.DirectI/OdoesnotprovideanyflexibilityinI/Oprogramming,sinceonlyasmallsetofspecialI/OinstructionsareallowedtoreferenceI/Oregisters.● formemory-mappedI/O,theprocessorusesthesameaddresslinestoaccessalltheaddressableI/Oregistersandthesamedatalinestosend/receivedatato/formtheseregisters.ThissimplifiestheconnectionbetweenI/Oportandtheprocessor,andthusleadstoalow-costhardwaredesignandimplementation.FordirectI/O,theconnectionbetweenI/Oportsandtheprocessormaybemoreexpensive.Thisisbecauseeither(1)specialhardwareisneededtoimplementseparateI/Oaddresslinesor(2)whenmemoryaddresslinesareusedforI/O;aspecialflagisneeded,indicatingthattherequestedaddressisforanI/Ooperation.●InspiteoftheadvantageofusingordinarymemoryreferenceinstructionstoaccessI/Oregisters,memory-mappedI/OmaycomplicatethecontrolunitdesigninregardstotheimplementationofI/O-relatedinstructions.ThisisbecauseusuallytheI/Obuscyclesneedtobelongerthantheequivalentmemorybuscycles,andthismeansthatthedesignofdifferenttimingcontrollogicisrequired.Thiscanbeusedtoexplainwhymemory-mappedI/Obenefitsprogrammers,butnotelectronicsengineers.● DirectI/Oaddressinghasanotheradvantageovermemory-mappedI/Ointhatlow-leveldebuggingonadifferentiatedaddressingsystemmaybeeasier,becausebreak-pointsorerrortrapscanbeimposedmoregenerally.● withmemory-mappedI/O,I/Oregisterssharethesameaddressspacewithmainmemory;hence,thememoryspaceavailableforprogramsanddataisreduced.FordirectI/Oaddressing,I/Odoesnotsharememoryspacewithmainmemory,andasinglecontiguousmemoryspacecanbemaintainedandusedbyprogrammers.ProgrammedI/OProgrammedI/Orequiresthatalldatatransferoperationsbeputunderthecompletecontroloftheprocessorwhenexecutingprograms.Itissometimescalledpolling,becausetheprogramrepeatedlypolls(checks)thestatusflagofanI/Odevice,sothatitsinput/outputoperationcanbesynchronizedwiththeprocessor.AgeneralflowchartofsuchaprogramisshowninFigure1.TheprogramcontinuouslypollsthestatusofanI/Odevicetofindoutwhether(1)dataisavailableintheinputbufferor(2)theoutputdeviceisreadyforreceivingdatafromtheprocessor.Ifthestatusshows“available”theprogramwillexecuteadatatransferinstructiontocompletetheI/Ooperation;otherwise,thebusystatusoftheI/Odevicewillforcetheprogramtocirculateinabusy-waitingloopuntilthestatusbecomesavailable.Suchabusy-waitingloop,whichcontinuouslychecksthestatusofdataavailability(forinput)ordeviceavailability(forout-put),formsthetypicalprogramstructureofprogrammedI/O.Itisthistime-consumingbusy-waitingloopthatwastesprocessortimeandmakesprogrammedI/Overyinefficient.TheprocessormustbeinvolvedcontinuouslyintheentireI/Oprocess.Duringthistimeinterval,theprocessorcannotperformanyusefulcomputation,butonlyserveasingleI/Odevice.ForcertainslowI/Odevices,thisbusy-waitingloopintervalmaybelongenoughthattheprocessorcouldexecutemillionsofinstructionsbeforetheI/Oeventoccurs,e.g.,akeystrokeonakeyboard.TheoperationalmodelfprogrammedI/Ostatedaboveischaracterizedbythebusywaitingloopoftheprogram,duringwhichtheprocessorspendstimepollinganI/Odevice.Becauseofthededicationoftheprocessortoasingletask,thismodeofprogrammedI/Oiscalleddedicatedpollingorspinpolling.Althoughdedicatedpollingishighlyinefficient,sometimesitisnecessaryandevenunavoidable.Inaparticularcase,ifanurgenteventneedsanimmediateresponsewithoutdelay,thendedicatedpollingbyadedicatedprocessormaybethebestwaytohandleit.Oncetheexpectedeventhappens,theprocessorcantracttoitimmediately.Forexample,certainrealtimesystems(e.g.,radarechoprocessingsystems)requireareactiontoincomingdatathatissoquickthatevenaninterruptresponseistooslow.Undersuchacircumstance,onlyafastdedicatedpollingloopmaysuffice.AnothermodeofoperationofprogrammedI/Oiscalledintermittentpollingortimedpolling.Inthismode,theprocessormaypollthedeviceataregulartimedinterval,whichcanbeexpectedorprescheduled.Suchadevicecanbefoundinmanyembeddedsystemswhereaspecial-purposecomputerisusedforprocesscontrol,dataacquisition,environmentalmonitoring,trafficcounting,etc.thesedevices,whichmeasure,collect,orrecorddata,areusuallypolledperiodicallyinaregularscheduledeterminedbytheneedsoftheapplication.Suchamethodofintermittentpollingcanhelpsavetimelostinspinpollingandavoidthecomplexityofinterruptprocessing.However,itshouldbenotedthatintermittentpollingmaynotbeapplicableinsomespecialcases,inwhichthereisonlyonedevicetobepolledandthecorrectpollingratemustbeachievedwiththeassistanceofaninterrupt-drivenclock.Usingtimedpollinginthiscasewouldresultinsimplyswappingoneinterrupt-drivenclock.Usingtimepollinginthiscasewouldresultinsimplyswappingoneinterruptrequirementforanother.Interrupt-DrivenI/OInterrupt-drivenI/Oisameanstoavoidtheinefficientbusy-waitingloops,whichcharacterizeprogrammedI/O.InsteadofwaitingwhiletheI/Odeviceisbusydoingitsjobofinput/output,theprocessorcanrunotherprograms.WhentheI/Odevicecompletesitsjobanditsstatusbecomes“available”,itwillissueaninterruptrequesttotheprocessor,askingforCPUservice.Inresponse,theprocessorsuspendswhateveritiscurrentlydoing,inordertoattendtotheneedsofthatI/Odevice.Inrespondtoaninterruptrequest,theprocessorwillfirstsavethecontentsofboththeprogramcounterandthestatusregisterfortherunningprogram,andthentransferthecontroltothecorrespondinginterruptserviceroutinetoperformtherequireddatainput/outputoperation.Whentheinterruptserviceroutinehascompleteditsexecutionandifnomoreinterruptrequestsarepending,theprocessorwillresumetheexecutionofthepreviouslyinterruptedprogramandrestorethecontentsofthestatusesandprogramcounter.Theprocessorhardwareshouldchecktheinterruptrequestsignaluponcompletionofexecutionofeveryinstruction.Ifmultipledevicesissuetheirinterruptrequestsatthesametime,theprocessormustusesomemethodtochoosewhichonetoservicefirst,andthenservicealltheotherinterruptrequestsonebyonebyorderofpriority.OnlyafteralltheinterruptrequestshavebeenservicedwilltheCPUreturntotheinterrupteduserprogram.Inthisway,theprocessorcanservemanyI/Odevicesconcurrentlyandspendmoretimedoingusefuljobs,ratherthanrunningabusy-waitinglooptoserveasingledevice.Therefore,interruptI/Oisveryeffectiveinhandlingslowandmedium-speedI/Odevices.Furthermore,theconceptofaninterruptcanbegeneralizedtohandleanyeventcausedbyhardwareorsoftware,internallyorexternally.Thisgeneralproblemisreferredtoasexceptionprocessing.Ifmultipleinterruptrequestsareissuedbydifferentdevicesatthesametime,theprocessorshouldhavesomemeanstoidentifytheinterruptsourcesandhandletheirinterruptrequestsbysomepolicy,typicallybypriority.Onlyonerequestwiththehighestprioritycanbeservicedatthecurrenttime,whileallothersareputintoawaitingqueue.Uponthecompletionoftheserviceperformedbyaninterruptserviceroutine,theprocessorshouldsearchthewaitingqueueforallthependinginterruptrequests,oldornew,andcontinuetoservicethemonebyoneaccordingtotheirpriorities,untilthequeuebecomesempty.Onlywhenallthependinginterruptrequestshavebeenservicedcantheinterrupteduserprogramberesumed.Althoughthiscasecontainsmultipleinterruptrequests,itisstillasimplifiedcase.Theassumptionisthatalltheinterruptserviceroutinesmustbecompletedwithoutfurtherinterruption9(orso-calledpreemption)oncetheyhavebeenstartedoneafteranotherbytheprocessor.Aninterruptprocesssatisfyingthisassumptioniscalledanon-preemptiveinterrupt.Inreal-lifecircumstances,theprocessofinterrupt-drivenI/Ocanbemorecomplicatedthanthissimplifiedcase.Eachinterruptedserviceroutinerunningintheprocessorcanbepreempted(interrupted)byanewlyarrivedinterruptrequest,whichhasahigherprioritythanthecurrentone.Thiscircumstancewillcausethemainprogramandalltherequestedinterruptserviceroutinestohaveacomplicatedinterrelationship.Aninterruptprocessthatallowsaninterruptserviceroutinetobepreemptedbyahigher-priorityinterruptserviceroutineiscalledapreemptiveinterrupt.DirectMemoryAccessAlthoughinterruptI/OismoreefficientthantheprogrammedI/O,itstillsuffersfromarelativelyhighoverheadwithrespecttohandlingtheinterrupt.Thisoverheadincludesresolvingtheconflictamongmultipleinterruptrequests,savingandrestoringtheprogramcontexts,poolingforinterruptidentification,branchingto/fromtheinterruptserviceroutine,etc.Usinganinterruptisawastefulactivitythatcantakeseveralmicrosecondstocomplete.Directmemoryaccess(DMA)isamethodthatcaninput/outputablockofdatadirectlyto/formmainmemorywithaspeedofonedataitempermemorycycle,withoutcontinuousinvolvementoftheprocessor.TheentireprocessisimplementedbythehardwareofaDMAcontroller,whichtakestheplaceoftheprocessorandcommunicatesdirectlywithmainmemory.Asaresult,theblockdiagramofthecomputersystemchangesformprocessor-centeredtomemory-centered.Hence,fromtheviewpointofI/Oprocessing,theprocessorisnolongerthecenterofacomputer,butratherapartnerwithwhichtheI/Osubsystemcompetesformemorybuscyclestoinput/outputdataitemto/frommainmemory.However,aDMAcontrollerisdesignedtoexchangedatainblocks,soitworkswellwiththelarge-volumehigh-speedblock-orientedI/Odevices,suchashigh-speeddisksandcommunicationnetworks.TheDMAcontrollercanworkintwodifferentmodes.Normally,itworksconcurrentlywiththeprocessor,competingforindividualmemorybuscyclestoinput/outputsuccessivewordsofadatablock.IftheI/Ospeedisnotveryhigh,thememoryaccessesbytheprocessorandtheDMAcontrollercanbeinterwoven.Timeisaccruedonacycle-by-cyclebasis.NeithertheprocessornortheDMAcontrollercancontinuouslyuseallthememorybuscyclesduringanytimeinterval.ThisoperationalmodeoftheDMAcontrolleriscalledcyclestealing,sonamedbecausetheI/Osubsystemisessentially“stealing”memorybuscyclesfromtheprocessor.ThismodeintegratestheDMAmemoryaccessesintoCPUactivityandavoidsseriousdisruptionofthemainprocessing.Alternatively,forevenhigherI/Otransferspeed,DMAoperationsrequirebustime,whichcanbeallocatedinblockofcyclesknownasbursts.Duringaburstofmemorycycles,theprocessoristotallyexcludedfromaccessingmemory.TheDMAcontrollerisgivenexclusiveaccesstomainmemoryandcontinuouslyinputs/outputsblocksofdataataspeedcomparabletothememoryspeed.ThisoperationalmodeoftheDMAcontrolleriscalledtheblockorburstmode.ADMAcontrollerdesignedforthismodeofoperationusuallyincorporatesadatastoragebufferwithacapacitymatchingthesizeofatleastonedatablock.WhentheDMAcontrollerutilizesthememorybus,itcantransferadatablockdirectlybetweenitsdatastoragebufferandmainmemory.ThefollowingregistersarenecessaryfortheDMAtotransferablockofdata:●Databufferregister(DBR)－itcanbeimplementedastworegisters,oneforinputandtheotherforoutput,orevenasetofregisterscomprisingadatastoragebuffer.●DMAaddressregister(DAR)－usedtostorethestartingaddressofthememorybufferareawheretheblockofdataistobereadorwritten.●Wordcounter(WC)－thecontentsspecifythenumberofwordsintheblockofdataremainingtobetransferredanditisautomaticallydecrementedaftereachwordistransferred.●Control/statusregister(CSR)－usedbytheprocessortosendcontrolinformationtotheDMAcontrollerandtocollectthestatusesanderrorinformationoftheDMAcontrollerandtheI/Odevicesattachedtoit.Usingtheseregisters,theDMAcontrollerknowstheaddressesofthesourceanddestinationdatablocks,aswellasthequantityofdatatobetransferred.OncetheDMAcontrolleracquiresthememorybus,theblocktransferoperationcanbeperformedautonomouslyusingtheinformationcontainedintheseregisters,withoutthecontinuousinvolvementoftheprocessor.Besidestheabove-listedregisters,theDMAcontrollershouldcontainthecontrollogicofabusrequestfacility,whichperformsbusarbitrationusingthesignalsofDMArequest(DMAR)andDMAacknowledge(DMAA).BusarbitrationistheprocessofresolvingthecontentionamongmultipleconcurrentlyoperatingDMAcontrollersforacquisitionofthememorybus.TheselectionofthebusmasterisusuallybasedontheprioritiesofvariousDMDdevices.AmongdifferentDMAdevices,thepriorityorderarearrangedbythedegreeurgencyofthedevicesreceivingtheDMAservice,i.e.,accordingtotheirspeedrequirements.TherearetwoapproachestobusarbitrationforDMAdevices－centralizedanddistributed－whicharesimilartotheapproachesusedtoidentifyinterruptsourcesusingsignalsforinterruptrequest(INTR)andinterruptacknowledge(INTA).AlthoughthetransferofthedatablockisperformedbytheDMAwithoutinvolvementoftheprocessor,theoveralloperationoftheDMAcontrollerisstilldeterminedbytheCPUviainterrupts.Itservestwopurposesasfollows:(1)BeforetheDMAcontrollerstartsthedatatransfer,alltheregistersmustbeinitializedbytheprocessor.(2)WhentheDMAfinishesablocktransferoperation,itshouldinformtheprocessorofcompletionbyissuinganinterrupt,whichallowstheprocessortopost-processthedatainthememorybufferareaorhandlepossibleerrorconditions.Therefore,theDMAcontrolleroftenissuedinterruptrequest(INTR)andreceivesinterruptacknowledge(INTA)signals.DNArelievestheprocessorformtheburdenofI/Ofunction,exceptfortheinitializationofthetransferofparametersandthepost-processingofdata.Itisveryefficientwhenservinghigh-speedI/Odevices.However,theroleofDMAisnotlimitedtotheareaofinput/output.Incontemporarycomputersystems,DMAhasbeendevelopedintoageneraltechniqueoftime-sharingthemainmemorybandwidthbetweenI/OsubsystemprocessingandCPUprocessing.IntheI/Osubsystem,high-speedI/Odevices,suchasdisks,CD-ROMs,DVDs,graphics,videoequipment,andhigh-speednetworks,wanttosharemainmemorybandwidththroughtheDMA.Intheareaofcentralprocessingandthemainmemorysystem,(1)runningprograms,(2)theoperatingsystem,and(3)dynamicRAMrefreshingareallsharingthemainmemorybandwidth,DMAistheappropriatewaytoimplementthistime-sharing.Faster16-bitUltraDMAhasnowreplacedtheoutdated8-bitfacilities.CommerciallyavailableDMAcontrollerchipsnowoffermultiplechannels,allowingconcurrentdatatransfer.Forexample,onechannelcanbereservedforDRAMrefreshing;anotherchannelcanperformmemory-tomemoryblockmoves,etc.Tofurtherfreetheprocessorfromhandlingslowtasks,powerfulchannelprocessorshavebeendevelopedwithautonomouscapabilities,includingdevicepolling,channelprogramexecution,interruptactivationandDMAfordataandinstructions.Theyhavebecomeagrowingclassofsemi-independentco-processorscommunicatingwiththemainprocessor.Theycanbeassigneddedicatedtasks,suchasfloating-pointcalculations,graphicprocessing,networkcommunication,largedatabasemanagement,etc.Thegrowingbuscontentionproblem,duetotime-sharingmainmemorybandwidth,canbealleviatedbymoreeffectivelyusingcachememory.Forexample,inthePentiumprocessor,L1cacheallowstheCPUpipelinetocontinuefetchingandexecuting,aslongasthedemandcanbesatisfiedwithinstructionsheldlocallyinthecache.譯文：輸入/輸出訪問(wèn)在這一篇文章中，我們將會(huì)研究三種基本的輸入／輸出訪問(wèn)方法：程控I/O、中斷驅(qū)動(dòng)I/O以及直接存儲(chǔ)器訪問(wèn)（DMA）。區(qū)別這三個(gè)方法的關(guān)鍵問(wèn)題是處理器以怎樣的深度介入I/O操作。討論的重點(diǎn)是中斷驅(qū)動(dòng)I/O，這是因?yàn)樗幕A(chǔ)是中斷處理概念，而這是一個(gè)超過(guò)輸入輸出操作之外的普遍性問(wèn)題。學(xué)習(xí)中斷處理也有助于了解異常事件處理這一普遍性概念，其重要性不但有關(guān)I/O，而且有關(guān)計(jì)算機(jī)與其他系統(tǒng)控制函數(shù)的接口。I/O寄存器的尋址輸入/輸出設(shè)備經(jīng)過(guò)輸入/輸出端口與一個(gè)處理機(jī)通信。經(jīng)過(guò)輸入端口，處理器接受來(lái)自輸入／輸出裝置的數(shù)據(jù)。經(jīng)過(guò)輸出端口，處理器送數(shù)據(jù)給輸入／輸出裝置。每個(gè)輸入／輸出端口包含一個(gè)小的寄存器組,如數(shù)據(jù)緩沖寄存器(輸入緩沖器和/或輸出緩沖器)、狀態(tài)寄存器和控制寄存器。處理器必須有某種方法尋址這些寄存器，同時(shí)與它們通信。尋址輸入／輸出寄存器有存儲(chǔ)器映射輸入／輸出和直接輸入／輸出兩種方法。1．存儲(chǔ)器映射的輸入／輸出存儲(chǔ)器映射的輸入／輸出將輸入／輸出寄存器和存儲(chǔ)器一起映射到計(jì)算機(jī)系統(tǒng)的統(tǒng)一的住址空間。輸入／輸出寄存器共享主存儲(chǔ)器的同一個(gè)地址空間,但是被映射到一個(gè)特定的專為輸入／輸出預(yù)留的存儲(chǔ)器區(qū)段。因此，輸入／輸出寄存器能在普通的存儲(chǔ)器訪問(wèn)指令中得到尋址，好像它們就是主存儲(chǔ)器位置的一部份。在計(jì)算機(jī)的指令系統(tǒng)中沒(méi)有專門設(shè)計(jì)的輸入／輸出指令。任何訪問(wèn)這一地區(qū)中某個(gè)位置的指令便是一條輸入/輸出指令。任何的一條可以指定存儲(chǔ)器地址的指令都可以執(zhí)行輸入／輸出操作。摩托羅拉MC68000就是使用這種尋址方法的計(jì)算機(jī)系統(tǒng)的一個(gè)例子。2.直接輸入／輸出直接地向輸入／輸出寄存器尋址而不和主存儲(chǔ)器共享地址空間的尋址方法叫做直接輸入／輸出或輸入／輸出映射輸入／輸出。換句話說(shuō)，輸入／輸出寄存器不和主存儲(chǔ)器映射到同一個(gè)地址空間。每個(gè)輸入／輸出寄存器有一個(gè)獨(dú)立的地址空間。其結(jié)果是：訪問(wèn)主存儲(chǔ)器空間的指令不能夠作用于輸入/輸出。在計(jì)算機(jī)系統(tǒng)的指令系統(tǒng)中，必須為輸入／輸出操作設(shè)計(jì)專門的指令。在這些輸入／輸出指令中，必須用各自不同的標(biāo)號(hào)來(lái)尋址不同的輸入／輸出交換通道。它們被稱作端口號(hào)。輸入／輸出端口的輸入／輸出寄存器連接到系統(tǒng)輸入／輸出總線上，處理器經(jīng)過(guò)它可以直接訪問(wèn)輸入／輸出寄存器向/從輸入／輸出裝置發(fā)送/接收數(shù)據(jù)。使用端口號(hào)的方式和使用存儲(chǔ)器地址的方式相同，但不同的是端口號(hào)不是來(lái)自主存儲(chǔ)器的同一地址。Pentium是使用直接輸入／輸出尋址法的計(jì)算機(jī)系統(tǒng)的例子。它有64GB存儲(chǔ)地址空間(32位住址)，同時(shí)，還有一個(gè)64KB輸入／輸出地址空間(16位輸入／輸出住址/端口號(hào))。我們能依下列各項(xiàng)比較存儲(chǔ)器映射輸入／輸出和直接輸入／輸出：:● 存儲(chǔ)器映射輸入／輸出使用普通的存儲(chǔ)器訪問(wèn)指令訪問(wèn)輸入／輸出，因此它提供輸入／輸出編程的靈活性，并簡(jiǎn)化輸入/輸出軟件。直接輸入/輸出不具備輸入/輸出編程的靈活性，因?yàn)橹挥幸粋€(gè)小的特殊輸入／輸出指令被允許訪問(wèn)輸入／輸出寄存器?！?有存儲(chǔ)器映射輸入／輸出時(shí)，處理器使用相同的住址線訪問(wèn)所有的可尋址輸入／輸出寄存器和用相同的數(shù)據(jù)線向/從這些寄存器發(fā)送/接收數(shù)據(jù)。這樣簡(jiǎn)化了輸入／輸出端口和處理器之間的連接，因而導(dǎo)致廉價(jià)的硬件設(shè)計(jì)和實(shí)現(xiàn)。對(duì)于直接輸入／輸出，輸入／輸出端口和處理器之間的連接可能成本比較高。這是因?yàn)樾枰獙ｉT的硬件實(shí)現(xiàn)分開(kāi)的輸入／輸出住址線，或者當(dāng)存儲(chǔ)器地址線用于輸入／輸出的時(shí)候,需要一個(gè)特殊的標(biāo)志來(lái)指出所要求的住址是為了輸入／輸出操作的?！?盡管使用普通的存儲(chǔ)器訪問(wèn)指令訪問(wèn)輸入／輸出寄存器有它的優(yōu)點(diǎn)，但存儲(chǔ)器映射輸入／輸出可能會(huì)使控制器的設(shè)計(jì)較復(fù)雜一些，這涉及與輸入／輸出相關(guān)的指令的實(shí)現(xiàn)。這是因?yàn)橥ǔ］斎耄敵隹偩€周期比較等價(jià)的存儲(chǔ)器總線周期要長(zhǎng)一些，需要循環(huán)，而這意味著需要設(shè)計(jì)不同的時(shí)序控制邏輯。這能用來(lái)解釋為什么存儲(chǔ)器映射輸入／輸出有利于程序設(shè)計(jì)師,但是不是電子學(xué)工程師?！?直接輸入／輸出尋址有另一個(gè)高于存儲(chǔ)器映射輸入／輸出的優(yōu)點(diǎn)，即低級(jí)程序調(diào)試在用分開(kāi)尋址系統(tǒng)中可能要更容易些,因?yàn)閿帱c(diǎn)和錯(cuò)誤陷阱的設(shè)置比較通用。在存儲(chǔ)器映射輸入／輸出中，輸入／輸出寄存器和主存儲(chǔ)器共享同一地址空間，因此，程序和數(shù)據(jù)可以使用的存儲(chǔ)空間就減少了。對(duì)于直接輸入／輸出尋址，輸入／輸出不用和主存儲(chǔ)器共享存儲(chǔ)空間，可以維持一個(gè)單獨(dú)的連續(xù)存儲(chǔ)空間給程序員使用。程控輸入／輸出程控輸入／輸出需要全部數(shù)據(jù)操作處于處理機(jī)執(zhí)行程序的完全控制之下。因?yàn)槌绦蛑貜?fù)地巡查(檢查)一個(gè)輸入／輸出裝置的狀態(tài)標(biāo)志，所以有時(shí)它被稱為巡查，而且它的輸入/輸出操作能與處理器同步。程序不斷地巡查一個(gè)輸入／輸出裝置的狀態(tài)，以發(fā)現(xiàn)數(shù)據(jù)是否是已在輸入緩沖中或輸出裝置有沒(méi)有為接收從來(lái)自處理器的數(shù)據(jù)做好準(zhǔn)備。如果狀態(tài)顯示"已備好"，則程序?qū)?zhí)行一條數(shù)據(jù)傳輸指令以完成該輸入／輸出操作；否則，輸入／輸出裝置的忙碌狀態(tài)將會(huì)強(qiáng)迫程序在一個(gè)忙碌等待回路中循環(huán)，直到狀態(tài)變成“已備好”為止。這樣一個(gè)如此不斷地巡查“數(shù)據(jù)已備好“狀態(tài)(對(duì)于輸入)或巡查“設(shè)備已備好“狀態(tài)(對(duì)于輸出)，它形成程控輸入／輸出的典型程序結(jié)構(gòu)。正是這個(gè)浪費(fèi)時(shí)間的忙碌等待回路消耗處理機(jī)時(shí)間，而造成程控輸入／輸出效率很低。處理器必須連續(xù)的介入整個(gè)的輸入／輸出過(guò)程當(dāng)中。在這一時(shí)間間隔內(nèi)，處理器不能夠運(yùn)行任何的有用計(jì)算,而僅服務(wù)于單獨(dú)一個(gè)輸入／輸出裝置。對(duì)于某些慢速輸入／輸出裝置,這一忙碌等待回路的時(shí)間可能很長(zhǎng)，足夠處理機(jī)在輸入／輸出事件發(fā)生之前，運(yùn)行數(shù)以百萬(wàn)計(jì)指令,如在鍵盤上的一次按鍵動(dòng)作。上面敘述的程控輸入／輸出操作模式是以程序的忙碌等待回路為特征的,在它運(yùn)行時(shí)處理器花費(fèi)時(shí)間巡查一個(gè)輸入／輸出裝置。因?yàn)樘幚砥鲗Ｗ⒂谝粋€(gè)單一的作業(yè)，這種程控輸入／輸出模式被稱為專注式巡查或回旋式巡查。雖然專注式巡查十分低效,但是有時(shí)它是必需的，甚至是不可避免的。在一個(gè)特別的情形中，如果一件緊急的事件需要沒(méi)有延遲立即響應(yīng),則用一臺(tái)專門的計(jì)算機(jī)做專注式巡查可能是最好的處理方法。一旦預(yù)期的事件發(fā)生,處理器可以立刻反應(yīng)。舉例來(lái)說(shuō),某些實(shí)時(shí)系統(tǒng)(如雷達(dá)回波處理系統(tǒng))需要對(duì)收入的數(shù)據(jù)極快的反應(yīng)，甚至是一次中斷反應(yīng)都嫌太慢。在這樣的環(huán)境之下，只有專注式巡查回路才足夠應(yīng)付。程控輸入／輸出的另一個(gè)操作模式叫做間歇式巡查或定時(shí)巡查。在這一個(gè)模式中，處理器可在有規(guī)則的（預(yù)期的或事先規(guī)劃的）時(shí)間間隔巡查設(shè)備。這種設(shè)備在許多嵌入式系統(tǒng)中可以看到，其中一臺(tái)專用計(jì)算機(jī)用于過(guò)程控制、數(shù)據(jù)采集、環(huán)境監(jiān)測(cè)、流量計(jì)數(shù)等。這些設(shè)備量測(cè)、收集或記錄數(shù)據(jù),通常是按照有規(guī)則的時(shí)間表進(jìn)行周期性的巡查，其規(guī)劃由應(yīng)用對(duì)象的需要決定。這種間歇式巡查方法可以有助于節(jié)省回旋式巡查所浪費(fèi)的時(shí)間，并且避免中斷處理的復(fù)雜性。然而應(yīng)該注意，間歇式巡查可能不適用某些特別的情形,只有一個(gè)裝置被巡查而正確的巡查又一定要借助一個(gè)由中斷驅(qū)動(dòng)的時(shí)鐘才能得到。在這種情況使用定時(shí)巡查只能是簡(jiǎn)單的交替一次又一次中斷需求。中斷驅(qū)動(dòng)輸入／輸出中斷驅(qū)動(dòng)輸入/輸出是一種能避免程控輸入/輸出特有的低效忙碌等待回路的方法。當(dāng)輸入/輸出設(shè)備忙于它的輸入輸出作業(yè)時(shí)，處理機(jī)不是等待，而是可以運(yùn)行其他的程序。當(dāng)輸入/輸出設(shè)備完成它的作業(yè)而使其狀態(tài)變?yōu)椤耙褌浜谩睍r(shí)，它將向處理機(jī)發(fā)出一個(gè)中斷請(qǐng)求，要求CPU的服務(wù)。作為響應(yīng)，處理機(jī)掛起它正在做的任何工作，以便照顧該輸入/輸出設(shè)備的需要。為了響應(yīng)中斷請(qǐng)求,處理器將會(huì)首先為正在運(yùn)行中的程序保存好程序計(jì)數(shù)器和狀態(tài)計(jì)數(shù)器的內(nèi)容，然后轉(zhuǎn)移控制到對(duì)應(yīng)的中斷服務(wù)程序，以執(zhí)行要求的輸入/輸出操作。當(dāng)中斷服務(wù)程序已經(jīng)執(zhí)行完畢時(shí)，如果沒(méi)有更多的中斷請(qǐng)求在等待,處理器將恢復(fù)狀態(tài)寄存器和程序計(jì)數(shù)器的內(nèi)容，恢復(fù)執(zhí)行原先被中斷的程序。處理器的硬件應(yīng)該在每條指令執(zhí)行結(jié)束時(shí)檢查中斷請(qǐng)求信號(hào)。如果有多個(gè)裝置同時(shí)發(fā)行它們的中斷請(qǐng)求,處理器必須利用某些方法選擇哪一個(gè)首先服務(wù),然后再根據(jù)優(yōu)先權(quán)的次序逐個(gè)的服務(wù)所有其他的中斷請(qǐng)求。只有當(dāng)所有的中斷請(qǐng)求都已得到服務(wù)，CPU才返回被中斷的用戶程序。這樣，處理器能并發(fā)的服務(wù)于多個(gè)輸入／輸出裝置，而且用較多的時(shí)間做有用的工作,而不去運(yùn)行一個(gè)忙碌等待回路為單個(gè)裝置服務(wù)。因此,中斷驅(qū)動(dòng)輸入/輸出在處理慢速和中速輸入/輸出/設(shè)備方面是很有效的。此外，中斷的觀念可以被推廣到處理任何由硬件或軟件從內(nèi)部或外部產(chǎn)生的事件。這一普遍性問(wèn)題稱為異常事件處理。如果多個(gè)中斷請(qǐng)求有不同的設(shè)備同時(shí)發(fā)出,處理器應(yīng)該有某種方法識(shí)別中斷來(lái)源而且按照某種策略（典型的是按優(yōu)先權(quán)）處理它們的中斷請(qǐng)求?，F(xiàn)時(shí)只能有一個(gè)帶最高優(yōu)先權(quán)的請(qǐng)求可以得到服務(wù),所有其它的請(qǐng)求都放入一個(gè)候補(bǔ)等待的隊(duì)伍之內(nèi)。在中斷服務(wù)程序執(zhí)行服務(wù)完畢，處理器應(yīng)該搜索等待的隊(duì)列，找出所有正在等待中的舊的或新的中斷請(qǐng)求,并按照優(yōu)先權(quán)逐個(gè)繼續(xù)為它們服務(wù)，直到等待的隊(duì)伍變空為止。只有當(dāng)所有等待著的中斷請(qǐng)求都已經(jīng)得到服務(wù)，才會(huì)喚回被中斷的用戶程序。雖然這一個(gè)情形包含了多個(gè)中斷請(qǐng)求,但是它仍然是一個(gè)被單一化的情形。假定：所有的中斷服務(wù)程序一旦被處理器一個(gè)接一個(gè)的啟動(dòng)，它們便必須完成而不再由中斷或所謂搶占發(fā)生。滿足這一假設(shè)的中斷過(guò)程稱為非搶占中斷。在真實(shí)的環(huán)境中，中斷驅(qū)動(dòng)輸入／輸出的過(guò)程比這個(gè)簡(jiǎn)化過(guò)程更為復(fù)雜。每個(gè)正在處理機(jī)中運(yùn)行的中斷服務(wù)程序可以被新來(lái)的中斷請(qǐng)求所搶占（中斷），只需它的優(yōu)先權(quán)比現(xiàn)有的優(yōu)先權(quán)高。這一個(gè)環(huán)境將會(huì)引起主程序和所有被要求的中斷服務(wù)程序之間有一個(gè)復(fù)雜的相互關(guān)系。允許中斷服務(wù)程序被較高優(yōu)先權(quán)的中斷服務(wù)程序所強(qiáng)占的中斷過(guò)程叫做搶占中斷。直接存儲(chǔ)器訪問(wèn)雖然中斷驅(qū)動(dòng)輸入／輸出比被程控輸入／輸出有效率,但是它仍然受限于較高的與中斷處理有關(guān)的開(kāi)銷。這一開(kāi)銷包括解決多個(gè)中斷請(qǐng)求之中的沖突、保存和恢復(fù)程序現(xiàn)場(chǎng)、用于中斷辨認(rèn)的巡查、中斷服務(wù)程序的來(lái)回轉(zhuǎn)移等。使用中斷是一個(gè)浪費(fèi)的活動(dòng)，它費(fèi)時(shí)好幾個(gè)微秒才能完成。直接存儲(chǔ)器訪問(wèn)(DMA)是一個(gè)向/從主存儲(chǔ)器直接輸入輸出字塊的方法，速度是每一存儲(chǔ)周期一個(gè)數(shù)據(jù)項(xiàng)，而無(wú)需處理機(jī)的連續(xù)參與。整個(gè)過(guò)程由DMA控制器的硬件實(shí)現(xiàn),它代替處理器而直接與主存儲(chǔ)器通信。結(jié)果，計(jì)算機(jī)系統(tǒng)的框圖由以處理機(jī)為中心變?yōu)橐源鎯?chǔ)器為中心。因此，從輸入／輸出處理的觀點(diǎn)來(lái)看，處理器不再是計(jì)算機(jī)的中心,而只是一個(gè)伙伴，輸入／輸出子系統(tǒng)和它競(jìng)爭(zhēng)存儲(chǔ)器總線周期，向/從主存儲(chǔ)器輸入輸出數(shù)據(jù)。然而，DMA控制器是設(shè)計(jì)成以字塊交換數(shù)據(jù)，因此，它能很好的和大容量高速度面向字塊的輸入／輸出裝置,例如高速磁盤通信網(wǎng)絡(luò)，一起工作。.DMA控制器能在兩個(gè)不同的模式下工作。正常情況下，它與處理器并發(fā)的工作,競(jìng)爭(zhēng)零星的存儲(chǔ)器總線周期，以輸入輸出一個(gè)字塊的連續(xù)的字。如果輸入／輸出速度不是很高,處理器的存儲(chǔ)器訪問(wèn)和DMA控制器訪問(wèn)可以交叉進(jìn)行。時(shí)間可以在周期到周期的基礎(chǔ)上增加。在任何一個(gè)時(shí)間段，處理器或DMA控制器都不能連續(xù)的使用所有的存儲(chǔ)器總線周期。DMA控制器的這一操作模式叫做周期竊取。如此命名是因?yàn)檩斎耄敵鲎酉到y(tǒng)實(shí)質(zhì)上是從處理器“竊取”存儲(chǔ)器總線周期。這一個(gè)模式把直接內(nèi)存存取的存儲(chǔ)器訪問(wèn)整合在CPU活動(dòng)中，避免嚴(yán)重的打擾主要的處理任務(wù)。另一方面，對(duì)于更高的輸入／輸出傳輸率，直接內(nèi)存存取操作需要總線時(shí)間能安排在成塊的周期內(nèi)，這稱為爆發(fā)。在存儲(chǔ)周期的爆發(fā)中，處理器完全地被排斥在存儲(chǔ)器訪問(wèn)之外。直接內(nèi)存存取控制器被給與主存儲(chǔ)器的排他性訪問(wèn)，連續(xù)的輸入輸出數(shù)據(jù)字塊，其速度可以和存儲(chǔ)器速度相比較。直接內(nèi)存存取控制器的這一操作模式被稱為字塊模式或爆發(fā)模式。為這一操作模式設(shè)計(jì)的直接內(nèi)存存取控制器通常結(jié)合一個(gè)數(shù)據(jù)存儲(chǔ)緩沖器，其容量至少與一個(gè)字塊相匹配。當(dāng)DMA控制器利用存儲(chǔ)器總線時(shí)，它可以直接在它的數(shù)據(jù)存儲(chǔ)緩沖器和主存儲(chǔ)器之間交換一個(gè)字塊。下列各寄存器對(duì)于DMA傳輸一個(gè)字塊是必要的：●數(shù)據(jù)緩沖寄存器(DBR)——它可以實(shí)現(xiàn)為兩個(gè)寄存器,一個(gè)用于輸入，另一個(gè)用于輸出,或者甚至于一個(gè)寄存器組，組成一個(gè)數(shù)據(jù)存儲(chǔ)緩沖器。●DMA地址寄存器(DAR)——用來(lái)存放存儲(chǔ)器緩沖區(qū)（用來(lái)讀寫(xiě)字塊）的起始地址。●字計(jì)數(shù)器(WC)——由它的內(nèi)容指定字塊中余下尚待傳輸?shù)淖謹(jǐn)?shù)，每一個(gè)字傳輸以后字?jǐn)?shù)自動(dòng)減值?！窨刂?狀態(tài)寄存器(CSR)——處理器用來(lái)發(fā)送控制信息給直接內(nèi)存存取控制器并且收集直接內(nèi)存存取控制器和它所連輸入／輸出裝置的狀態(tài)和出錯(cuò)信號(hào)。利用這些寄存器,直接內(nèi)存存取控制器能知道源字塊和目的字塊,以及將要傳輸?shù)臄?shù)據(jù)量。一旦直接內(nèi)存存取控制器獲得了存儲(chǔ)器總線，便可以利用這些寄存器中包含的信息，自主地執(zhí)行字塊傳輸操作，而無(wú)需處理器的連續(xù)介入。在上列寄存器之外，直接內(nèi)存存取控制器還應(yīng)該包含總線請(qǐng)求設(shè)備的控制邏輯,它利用直接內(nèi)存存取請(qǐng)求(DMAR)和直接內(nèi)存存取回答(DMAA)信號(hào)執(zhí)行總線仲裁。總線仲裁是一個(gè)分解沖突的過(guò)程，用來(lái)解決多個(gè)并發(fā)請(qǐng)求之間產(chǎn)生的沖突，這些請(qǐng)求都想要操作直接內(nèi)存存取控制器以獲取存儲(chǔ)器總線?？偩€主方的確定通常是基于不同的DMA裝置具有的優(yōu)先權(quán)。在不同的直接內(nèi)存存取裝置之中，由裝置接收直接內(nèi)存存取服務(wù)的緊迫程度，也就是它們的速度需求，來(lái)安排優(yōu)先權(quán)次序。為直接內(nèi)存存取裝置進(jìn)行總線仲裁有兩個(gè)方法——集中式和分布式，它們和利用中斷請(qǐng)求(INTR)和中斷應(yīng)答(INTA)信號(hào)以辨認(rèn)中斷源的方法是相似的。雖然直接內(nèi)存存取執(zhí)行字塊傳輸沒(méi)有處理機(jī)參加,但是直接內(nèi)存存取控制器的總體操作仍然是由CPU通過(guò)中斷來(lái)決定的。它有兩個(gè)目的：(1)在直接內(nèi)存存取控制器啟動(dòng)數(shù)據(jù)傳輸之前，所有的寄存器必須由處理器設(shè)定初值；(2)當(dāng)直接內(nèi)存存取完成一個(gè)字塊傳輸操作時(shí),它應(yīng)該發(fā)出一個(gè)中斷告知處理器操作完成，以允許處理器在存儲(chǔ)器緩沖區(qū)進(jìn)行數(shù)據(jù)的后處理或者處理可能的錯(cuò)誤情況。因此，直接內(nèi)存存取控制器時(shí)常發(fā)出中斷請(qǐng)求(INTR)和接受中斷的回答(INTA)信號(hào)。DMA減輕處理器在輸入／輸出功能上的負(fù)擔(dān),但叁數(shù)傳輸初始化和數(shù)據(jù)的后處理除外。當(dāng)服務(wù)高速的輸入／輸出裝置的時(shí)候，這是非常有效的。然而，直接內(nèi)存存取的作用并不限于輸入輸出區(qū)域。在現(xiàn)代的計(jì)算機(jī)系統(tǒng)中，直接內(nèi)存存取已經(jīng)發(fā)展為一個(gè)通用的技術(shù)，它在輸入／輸出子系統(tǒng)處理和CPU處理之間進(jìn)行主存儲(chǔ)器帶寬的分時(shí)。在輸入／輸出子系統(tǒng)中，高速的輸入／輸出裝置，像磁盤，CD-ROM，DVD，圖像，視頻設(shè)備和高速網(wǎng)絡(luò)都要經(jīng)過(guò)直接內(nèi)存存取分享主主存儲(chǔ)器的帶寬。在中央處理和主存儲(chǔ)器范圍，運(yùn)行中的程序、操作系統(tǒng)以及動(dòng)態(tài)隨機(jī)存取儲(chǔ)存器的再生都要分享主存儲(chǔ)器帶寬。直接內(nèi)存存取是一個(gè)適當(dāng)?shù)姆椒▉?lái)實(shí)現(xiàn)這種分時(shí)。比較快速的16位UltraDMA現(xiàn)在已經(jīng)代替舊式的