基于HDL的組合邏輯電路實(shí)驗(yàn)

基于HDL的組合邏輯電路實(shí)驗(yàn)一、 實(shí)驗(yàn)?zāi)康?. 學(xué)習(xí)使用ISE13.4軟件生成一個(gè)新工程文件；2. 學(xué)習(xí)使用HDL進(jìn)行電路設(shè)計(jì)；3. 學(xué)會(huì)編輯頂層文件和用戶約束文件；4. 熟悉仿真、綜合、實(shí)現(xiàn)及FPGA配置等；5. 熟悉在Basys2開發(fā)板上的簡單外圍設(shè)備的控制。二、實(shí)驗(yàn)內(nèi)容組合邏輯Ⅰ1. 使用HDL設(shè)計(jì)一個(gè)新的邏輯功能：y=~(ab+cd)并驗(yàn)證。HDL源文件：modulegates(inputa,inputb,output[5:0]z);assignz[5]=a&b;assignz[4]=~(a&b);assignz[3]=a|b;assignz[2]=~(a|b);assignz[1]=a^b;assignz[0]=~(a^b);endmodule約束文件：NET"a"LOC=P11;NET"b"LOC=L3;NET"z[0]"LOC=M5;NET"z[1]"LOC=M11;NET"z[2]"LOC=P7;NET"z[3]"LOC=P6;NET"z[4]"LOC=N5;NET"z[5]"LOC=N4;仿真文件：modulegatestest; //Inputs rega; regb; //Outputs wire[5:0]z; //InstantiatetheUnitUnderTest(UUT) gatesuut( .a(a), .b(b), .z(z) ); initialbegin //InitializeInputs a=0; b=0; //Wait100nsforglobalresettofinish #200;a<=0;b<=1;#200; a<=1;b<=0; #200; a<=1;b<=1; //Addstimulushere endendmodule仿真波形2. 設(shè)計(jì)一個(gè)4選1多路選擇器，并在開發(fā)板上驗(yàn)證。HDL源文件：modulecompare4(inputwire[1:0]s,inputwirea,b,c,d,outputregy);always@*case(s)2'b00:y=a;2'b01:y=b;2'b10:y=c;default:y=d;endcaseendmoduleEndmodule約束文件：NET"d"LOC="F3";NET"c"LOC="G3";NET"b"LOC="B4";NET"a"LOC="K3";NET"s[1]"LOC="L3";NET"s[0]"LOC="P11";NET"y"LOC="G1";仿真文件：modulecompare4test; //Inputs reg[1:0]s; rega; regb; regc; regd; //Outputs wirey; //InstantiatetheUnitUnderTest(UUT) compare4uut( .s(s), .a(a), .b(b), .c(c), .d(d), .y(y) ); initialbegin //InitializeInputs s=0; a=0; b=0; c=0; d=0;#100;s=2'b00; a=1;#100;a=0;#50;a=1; #100;s=2'b01; b=0;#100;b=1;#50;b=1; #100;s=2'b10; c=1;#100;c=1;#50;c=0; #100;s=2'b11; d=1;#100;d=0;#50;d=1; //Addstimulushere endendmodule仿真波形：組合邏輯Ⅱ1. 完成四位數(shù)碼管動(dòng)態(tài)現(xiàn)顯示設(shè)計(jì)，實(shí)現(xiàn)8個(gè)SW輸入的兩位十六進(jìn)制數(shù)對應(yīng)的十進(jìn)制數(shù)在數(shù)碼管上顯示。1） HDL源文件x7heg4.vmodulelcd8(inputwireclk,clr,inputwire[3:0]hex1,hex0,outputreg[3:0]an,outputreg[6:0]sseg);reg[19:0]clkdiv;reg[3:0]hex_in;always@(posedgeclk,posedgeclr)beginif(clr==1)clkdiv<=0;elseclkdiv<=clkdiv+1;endalways@(*)case(clkdiv[19:18])2'b00:begin an=4'b1110; hex_in=hex0; end 2'b01:begin an=4'b1101; hex_in=(hex0>4'h9)?4'h1:4'h0; end2'b10:begin an=4'b1011; hex_in=hex1; end2'b11:begin an=4'b0111; hex_in=(hex1>4'h9)?4'h1:4'h0; end endcasealways@(*)case(hex_in)4'h0:sseg[6:0]=7'b0000001;4'h1:sseg[6:0]=7'b1001111;4'h2:sseg[6:0]=7'b0010010;4'h3:sseg[6:0]=7'b0000110;4'h4:sseg[6:0]=7'b1001100;4'h5:sseg[6:0]=7'b0100100;4'h6:sseg[6:0]=7'b0100000;4'h7:sseg[6:0]=7'b0001111;4'h8:sseg[6:0]=7'b0000000;4'h9:sseg[6:0]=7'b0000100;4'ha:sseg[6:0]=7'b0000001;4'hb:sseg[6:0]=7'b1001111;4'hc:sseg[6:0]=7'b0010010;4'hd:sseg[6:0]=7'b0000110;4'he:sseg[6:0]=7'b1001100;4'hf:sseg[6:0]=7'b0100100;endcaseendmodule2） 約束文件x7heg4.ucfNET"sseg[6]"LOC="L14";#Bank=1,Signalname=CANET"sseg[5]"LOC="H12";#Bank=1,Signalname=CBNET"sseg[4]"LOC="N14";#Bank=1,Signalname=CCNET"sseg[3]"LOC="N11";#Bank=2,Signalname=CDNET"sseg[2]"LOC="P12";#Bank=2,Signalname=CENET"sseg[1]"LOC="L13";#Bank=1,Signalname=CFNET"sseg[0]"LOC="M12";#Bank=1,Signalname=CGNET"an[3]"LOC="K14";#Bank=1,Signalname=AN3NET"an[2]"LOC="M13";#Bank=1,Signalname=AN2NET"an[1]"LOC="J12";#Bank=1,Signalname=AN1NET"an[0]"LOC="F12";#Bank=1,Signalname=AN0NET"clk"LOC="B8";#Bank=0,Signalname=MCLKNET"clr"LOC="G12";#Bank=0,Signalname=BTN0NET"hex1[3]"LOC="N3";#Bank=2,Signalname=SW7NET"hex1[2]"LOC="E2";#Bank=3,Signalname=SW6NET"hex1[1]"LOC="F3";#Bank=3,Signalname=SW5NET"hex1[0]"LOC="G3";#Bank=3,Signalname=SW4NET"hex0[3]"LOC="B4";#Bank=3,Signalname=SW3NET"hex0[2]"LOC="K3";#Bank=3,Signalname=SW2NET"hex0[1]"LOC="L3";#Bank=3,Signalname=SW1NET"hex0[0]"LOC="P11";#Bank=2,Signalname=SW02.（2）實(shí)現(xiàn)了兩個(gè)四位二進(jìn)制加法。HDL源文件：entityadderisPORT(CIN:INSTD_LOGIC;A,B:INSTD_LOGIC_VECTOR(3DOWNTO0);S:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);endadder;architectureBehavioralofadderisSIGNALSINT:STD_LOGIC_VECTOR(4DOWNTO0);beginSINT<=('0'&A)+B+CIN;S<=SINT(3DOWNTO0);COUT<=SINT(4);endBehavioral;約束文件：NET"a[0]"LOC=P11;NET"a[1]"LOC=L3;NET"a[2]"LOC=K3;NET"a[3]"LOC=B4;NET"b[0]"LOC=G3;NET"b[1]"LOC=F3;NET"b[2]"LOC=E2;NET"b[3]"LOC=N3;NET"c4"LOC=G1;NET"s[0]"LOC=P4;NET"s[1]"LOC=N4;NET"s[2]"LOC=N5;NET"s[3]"LOC=P6;仿真文件：LIBRARYieee;USEieee.std_logic_1164.ALL;--Uncommentthefollowinglibrarydeclarationifusing--arithmeticfunctionswithSignedorUnsignedvalues--USEieee.numeric_std.ALL;ENTITYtestISENDtest;ARCHITECTUREbehaviorOFtestIS--ComponentDeclarationfortheUnitUnderTest(UUT)COMPONENTadderPORT(CIN:INstd_logic;A:INstd_logic_vector(3downto0);B:INstd_logic_vector(3downto0);S:OUTstd_logic_vector(3downto0);COUT:OUTstd_logic);ENDCOMPONENT;--InputssignalCIN:std_logic:='0';signalA:std_logic_vector(3downto0):=(others=>'0');signalB:std_logic_vector(3downto0):=(others=>'0'); --OutputssignalS:std_logic_vector(3downto0);signalCOUT:std_logic;--Noclocksdetectedinportlist.Replace<clock>belowwith--appropriateportnameBEGIN --InstantiatetheUnitUnderTest(UUT)uut:adderPORTMAP(CIN=>CIN,A=>A,B=>B,S=>S,COUT=>COUT);--Stimulusprocessstim_proc:processbegin A<="0000"