序列檢測器仿真 verilog

0101/110序列檢測器仿真實(shí)驗(yàn)?zāi)康氖煜odelsim仿真軟件的使用方法，了解狀態(tài)機(jī)的建模方法，使用ModelSim仿真QuartusII工程。實(shí)驗(yàn)內(nèi)容用HDL語言的輸入方式，實(shí)現(xiàn)0101/110序列檢測器。用modelsim進(jìn)行仿真下載至DE0開發(fā)板上觀察實(shí)驗(yàn)結(jié)果代碼分析（以0101序列檢測器為例）1）狀態(tài)圖如下:1）狀態(tài)圖如下:圖3.10101（左）/110（右）序列檢測狀態(tài)圖2）主模塊中首先定義了本次實(shí)驗(yàn)的所有輸入輸出接口及各個(gè)狀態(tài)。其中，因?yàn)橛?種狀態(tài)，所以current為2位。//0101Sequentialdetectormodulelab1a（vin,cp,ncr,vout）;inputvin,cp,ncr;outputvout;regvout;reg[1:0]current,next;parameters0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;3）然后設(shè)置異步清零，在cp上升沿則沿觸發(fā)器狀態(tài)翻轉(zhuǎn)。always@(posedgecpornegedgencr)beginif(~ncr)current<=s0;elsecurrent<=next;end接著編寫組合邏輯部分，設(shè)定下一狀態(tài)產(chǎn)生和輸出的信號(hào)。always@(currentorvin)beginnext=2'bxx;case(current)s0:beginnext=(vin==1)?s0:s1;ends1:beginnext=(vin==1)?s2:s1;ends2:beginnext=(vin==1)?s0:s3;ends3:beginnext=(vin==1)?s2:s1;endendcaseend最后為輸出部分，本程序中設(shè)置讓輸出信號(hào)經(jīng)過一個(gè)寄存器再輸出，可以消除vout信號(hào)中的毛刺。always@(posedgecpornegedgencr)beginif(~ncr)vout=1'b0;elsebeginvout=1'b0;case(current)s0,s1,s2:vout=1'b0;s3:if(vin==1)vout=1'b1;elsevout=1'b0;endcaseendendendmodule測試模塊中同樣先定義了各個(gè)變量，并將它們與主模塊一一對(duì)應(yīng)后進(jìn)行初始化。moduletest();regcp,clr,en;wireq;lab1ad(.cp(cp),.ncr(clr),.vin(en),.vout(q));initialbegincp=0;clr=0;en=0;end接著設(shè)置各信號(hào)波形：clr在20個(gè)單位時(shí)間后變?yōu)?,en的數(shù)據(jù)變?yōu)橛行В琧p,,en則分別在每10個(gè)和16個(gè)單位時(shí)間翻轉(zhuǎn)一次。在420個(gè)單位時(shí)間后仿真停止。initialbegin#20clr=1;#400$stop;endalways#10cp=~cp;always#16en=~en;endmodule實(shí)驗(yàn)步驟1)打開Modelsim，出現(xiàn)歡迎界面點(diǎn)擊Jumpstart

：ra/：ra/Ta/國：ra/：ra/：ra/ira;：ra/iray'.ra/:ra/國：ra/ira;：ra/：ra/Ta/國：ra/：ra/：ra/ira;：ra/iray'.ra/:ra/國：ra/ira;irayiray間：rayira;：ra/MIMPORTANTInformationFLEXnervlO.8.5:MentorGraphicsLicensingMSLv2007.3withMGLSv8.50.5andPCLS2007.291IAccesscomprehensiveModelSimdocumentation:SelectHelp>ModelSimPDFBookcase:ra.jrayirayira.*Don'tshowthisdialogagainSelectJumpstarttouseF^lodelSimnow!CJumpstart^)Close點(diǎn)擊CreateaProject新建一個(gè)工程MWelcometoModelSimWelcometoModelSimaPiwkctsourceMokldlJilllI'iuJLlescontainsimulationdetailslikecompilesettings,sourcefiles,orlibraries.TheProjectManageralsoletsvouincludereferencestosharedglobalfiles.StartheretocreateanewModelSimproject.source,OpenaProjectYourmostrecentprojectisopenedwhenyoustartModelSim.StarthereifyouRdliketoopenanolderproject.Close設(shè)置好工程名和路徑后點(diǎn)擊OK點(diǎn)擊CreateNewFile選擇文件類型為Verilog雙擊文件名，寫好程序后用右鍵單擊文件，選擇CompileAllLayoutWindow成功后，文件名右邊的Status會(huì)變?yōu)榇蜚^^ModelSimALTERASTARTEREDITION6.5b-CustomO]Project-Fi/homev-'orkyT^odelsimylablylab1—：?：?：?：?：?：?=：±1團(tuán)X|statu」Typ已|o「de|wiudified一/Verilog107/26/1110:(2)選擇Simulate=>StartSimulation

Dnie,r.,ork.,T'1odesim'ab1'ame/Veriloglabltest.vAddProjectToolsLsFileEditViewCoinpile信tmtLi』Typ^DesignLayoutWindowDnie,r.,ork.,T'1odesim'ab1'ame/Veriloglabltest.vAddProjectToolsLsFileEditViewCoinpile信tmtLi』Typ^DesignOptimizationRun;meOptionsBreakEndSimulationir.odE.LeIdbL□二tp二tViregvoj.treg；L:0parair.ete:always3beginStartSimulation...mProject-F:/homeworK/Modelsim/lab1/司扇labl.vpModelSimALTERASTARTEREDITION6.5b-Simulate選擇所需的的測試文件點(diǎn)擊OK后如下圖點(diǎn)擊View=>Wave在Object中添加信號(hào)然后點(diǎn)擊RunAll開始仿真ModelSimBALTERASTARTEK'EDITION6.5b-CustomAlterFileEditView匚ciirpil已|AddObj已ct.sToolsLayoutWindowH已IpDesignOptimization...項(xiàng)您女i/.龜蠡￡K通|壘W(wǎng)i腳StartSimulation...RuntimeOptions...RunRun100捋引m寸Ins拍ne二j-#test±Jd卜?#INmAL#S■-4.#INmAL#13Break.Run-AllDesignunittestlablatesttestGALWAYS#18test:^ALWAYS^19testIE^vsim_capadty^rEndSimulationContinueModuleModuleProcessProcessProcessProcessForeign+日o:=?.■+acc=..■+acc=..Run-MextStepSt