MB 原理方塊圖

1、 MB 原理方塊圖.主板架構(gòu).總線介紹.GMCH和ICH功能概述Aaj.XuTel:8268一、主板架構(gòu) 北橋、南橋(Northbridge/Southbridge)結(jié)構(gòu)廣泛應(yīng)用于目前幾乎所有的PC機(jī)主板。傳統(tǒng)的南北橋結(jié)構(gòu)中，北橋(就是主板上靠近CPU插槽的一顆大芯片)負(fù)責(zé)與CPU的聯(lián)系并控制內(nèi)存、AGP、PCI接口，相關(guān)的數(shù)據(jù)在北橋內(nèi)部傳輸；南橋負(fù)責(zé)I/O接口以及IDE設(shè)備的控制等。不過Intel從810開始摒棄了南北橋橋的結(jié)構(gòu)。而采用了GMCH(AGP內(nèi)存控制中心)+ICH(I/O控制中心)的HubArchitecture結(jié)構(gòu)。使得內(nèi)部的傳輸速度加快了不少，代表著主板芯片組的發(fā)展方向。 根

2、據(jù)INTEL不同的芯片組我們作如下幾種結(jié)構(gòu)分析主板的架構(gòu)1）INTEL 440架構(gòu)2） INTEL 810 架構(gòu)3） INTEL 815架構(gòu). 5)INTEL 845架構(gòu). 7) INTEL 865架構(gòu). 8)INTEL 875架構(gòu). 9)INTEL 915架構(gòu). 10)INTEL 925架構(gòu). 11）INTEL 945架構(gòu).12）INTEL955 架構(gòu) 13)INTEL 975架構(gòu). 由于INTEL系列架構(gòu)在這幾年變化較快，我就拿目前廠內(nèi)比較具有代表性的915系列作個(gè)介紹，以作拋磚引玉之用。1. INTEL 915架構(gòu)AC97/Intel High Definition Audio Code

3、cIntel PCI Express Gigabit EthernetIntel Pentium 4 Processor or Intel Celeron D Processor Intel 82915P MCHDDR or DDR2DDR or DDR2DDR or DDR2DDR or DDR2Graphic CardDisplayUSB 2.0 8 ports 480Mb/sIDE4 SATA Ports 150MB/sPCI Express X1GPIOPower ManagementClock GenerationLAN Connect/ASFSystem Management (T

4、CO)SMBUS 2.0/I2CSeven PCI MastersFlash BIOSSIO Intel ICH6X533/800MHz FSBChannel AChannel BPCI Express X16DMI InterfacePCI BUSLPC InterfaceIntel Pentium 4 Processor or Intel Celeron D ProcessorDisplayFlash BIOSSIOLPC InterfaceDisplayDisplayAC97 3 Codec Support Intel 82915G MCHDDR or DDR2DDR or DDR2DD

5、R or DDR2DDR or DDR2Graphic CardUSB 2.0 8 ports 480Mb/s2 ATA 100 Port4 SATA Ports 150MB/sPCI Express X1GPIOPower ManagementClock GenerationLAN Connect/ASFSystem Management (TCO)SMBUS 2.0/I2CSeven PCI Masters Intel ICH6533/800MHz FSBChannel AChannel BPCI Express X16DMI InterfacePCI BUSVGAAnalog Displ

6、ayADD2 CardSDVO續(xù)二、1.FSB（HOST）BUS FSBFront Side Bus前端總線也就是以前所說的CPU總線，由于在目前的各種主板上前端總線頻率與內(nèi)存總線頻率相同所以也是 CPU與內(nèi)存以及L2 Cache（僅指Socket 7主板）之間交換數(shù)據(jù)的工作時(shí)鐘由于數(shù)據(jù)傳輸最大帶寬取決所同時(shí)傳輸?shù)臄?shù)據(jù)位寬度和傳輸頻率即數(shù)據(jù)帶寬=（總線頻率(數(shù)據(jù)寬度）/8 由此可見前端總線速率將影響電腦運(yùn)行時(shí)CPU與內(nèi)存、（L2 Cache）之間的數(shù)據(jù)交換速度，實(shí)際也就影響了電腦的整體運(yùn)行速度 2.ISA BUS ISAIndustrial Standard Architecture Bus,

7、 總線-工業(yè)標(biāo)準(zhǔn)體系結(jié)構(gòu)總線.3. PCI BUS .PCIPeripheral Component Interconnection總線-外設(shè)部件互連總線該標(biāo)準(zhǔn)是由Intel,IBM,DEC公司所制的PCI Bus與CUP中間經(jīng)過一個(gè)橋接器電路不直接與CPU相連的總線,故其穩(wěn)定性與匹配性較差,提升了CPU的工作效率,其擴(kuò)展槽可達(dá)到三個(gè)以上為32Bit/64Bit的總線是目前主板及外圍設(shè)備使用的的標(biāo)準(zhǔn)接口.4. AGP BUS AGPAccelerated Graphics Port總線-加速圖形控制端口其主要的結(jié)構(gòu)是在使用AGP芯片的顯示卡與主存之間建立專用通道,讓影像和圖形數(shù)據(jù)直接傳送到顯示

8、卡而不需要經(jīng)過PCI總線AGP總線為32bit數(shù)據(jù)和66Mhz的總線速度比PCI總線快為PCI總線的四倍,是在Pentium III CPU和真正32Bit的Windows操作系統(tǒng)環(huán)境之下一展身手,發(fā)揮其功能的主要結(jié)構(gòu)5.USB BUS USBUniversal Serial Bus通用串行總線.USB總線是由Intel.Microsoft.等七大領(lǐng)導(dǎo)世界電腦硬件和軟件的大公司所主導(dǎo),解決各種外圍設(shè)備接頭不統(tǒng)一的問題,可接127個(gè)外圍設(shè)備的標(biāo)準(zhǔn)接口.6. PCI Express BUS PCI Express BUS 屬于第三代總線架構(gòu)，數(shù)據(jù)傳輸量大，單向傳輸達(dá)到250MB/s/x。PCI E

9、xpress總線是一種點(diǎn)對(duì)點(diǎn)串行連接的設(shè)備連接方式，點(diǎn)對(duì)點(diǎn)意味著每一個(gè)PCI Express設(shè)備都擁有自己獨(dú)立的數(shù)據(jù)連接，各個(gè)設(shè)備之間并發(fā)的數(shù)據(jù)傳輸互不影響。三、GMCH和ICH功能概述 1. GMCH 拿Intel的D915P來說，它有下列功能：Processor Interface One Intel Pentium 4 processor or Intel Celeron D processor including 775-Land package. Supports Pentium 4 processor FSB interrupt delivery 533 MT/s (133 MHz

10、) FSB and 800 MT/s (200 MHz) FSB Supports Hyper-Threading Technology (HT Technology) FSB Dynamic Bus Inversion (DBI) 32-bit host bus addressing for access to 4 GB of memory space 12-deep In-Order Queue 1-deep Defer Queue GTL+ bus driver with integrated GTL termination resistors Supports a Cache Line

11、 Size of 64 bytes System Memory One or two 64-bit wide DDR/DDR2 SDRAM data channels Bandwidth up to 8.5 GB/s (DDR/DDR2 533) in dual-channel Interleaved mode. Non-ECC memory only. 256-Mb, 512-Mb and 1-Gb DDR/DDR2 technologies Only x8, x16, DDR/DDR2 devices with four banks and also supports eight bank

12、, 1-Gbit DDR2 devices. Opportunistic refresh Up to 64 simultaneously open pages (four ranks of eight bank devices* 2 channels) SPD (Serial Presence Detect) scheme for DIMM detection support Suspend-to-RAM support using CKE Supports configurations defined in the JEDEC DDR/DDR2 DIMM specification only

13、 PCI Express Graphics Interface One x16 PCI Express port Compatible with the PCI Express Base Specification revision 1.0a Integrated Graphics Device (82915G only) Core frequency of 333 MHz High-Quality 3D Setup and Render Engine High-Quality Texture Engine Video DVD/PC-VCR 3D Graphics Rendering Enha

14、ncements 2D Graphics Video Overlay Multiple Overlay Functionality Analog Display Support (82915G only) 400 MHz Integrated 24-bit RAMDAC Up to 2048x1536 85 Hz refresh Hardware Color Cursor Support DDC2B Compliant Interface Digital Display Support (82915G only) Two SDVO ports multiplexed with PCI Expr

15、ess Graphics Interface 200 MHz dot clock on each 12-bit interface Can combine two channels to form one larger interface Flat panels up to 2048x1536 85Hz or digital CRT/HDTV at 1920 x1080 85Hz Dual Independent Display options with digital display Multiplexed Digital Display Channels (Supported with A

16、DD2 Card). Supports TMDS transmitters or TV-Out encoders ADD2 card uses PCI Express Graphics x16 connector DMI Interface A chip-to-chip connection interface to Intel ICH6 2 GB/s point-to-point DMI to ICH6 (1 GB/s each direction) 100 MHz reference clock (shared with PCI Express Graphics Attach). 32-b

17、it downstream addressing Messaging and Error Handling 2. ICH ICH 作為主板IO的控制中心，功能繁多，以ICH6為例，它有下列功能： New: Direct Media Interface10 Gb/s each direction, full duplexTransparent to software New: PCI Express*4 PCI Express root portsFully PCI Express 1.0a compliantCan be statically configured as 4x1, or 1x4

18、 (Enterprise applications only)Two virtual channel support for full isochronous data transfersSupport for full 2.5 Gb/s bandwidth in each direction per x1 laneModule based Hot-Plug supported (e.g., ExpressCard*) PCI Bus InterfaceSupports PCI Rev 2.3 Specification at 33 MHzNew: Seven available PCI RE

19、Q/GNT pairsSupport for 64-bit addressing on PCI using DAC protocol New: Integrated Serial ATA Host ControllerFour ports.Data transfer rates up to 1.5 Gb/s (150 MB/s).Integrated AHCI controller (ICH6R/ICH6RW Only) Integrated IDE ControllerIndependent timing of up to two drivesUltra ATA/100/66/33, BMI

20、DE and PIO modesTri-state modes to enable swap bayNew: Intel High Definition Audio InterfacePCI Express endpointIndependent Bus Master logic for eight general purpose streams: four input and four outputSupport three external CodecsSupports variable length stream slotsSupports multichannel, 32-bit sa

21、mple depth, 192 kHz sample rate outputProvides mic array supportSupports memory-based command/response transportAllows for non-48 kHz sampling outputSupport for ACPI Device States AC-Link for Audio and Telephony CODECsSupport for three AC 97 2.3 codecs.Independent bus master logic for 8 channels (PC

22、M In/Out, PCM 2 In, Mic 1 Input, Mic 2 Input, Modem In/Out, S/PDIF Out)Support for up to six channels of PCM audio output (full AC3 decode)Supports wake-up events USB 2.0Includes four UHCI Host Controllers,supporting eight external portsIncludes one EHCI Host Controller that supports all eight ports

23、Includes one USB 2.0 High-speed Debug PortSupports wake-up from sleeping states S1S5Supports legacy Keyboard/Mouse software Integrated LAN ControllerIntegrated ASF Management ControllerWfM 2.0 and IEEE 802.3 CompliantLAN Connect Interface (LCI)10/100 Mb/s Ethernet Support Power Management LogicACPI

24、2.0 compliantACPI-defined power states C1, S1, S3S5ACPI Power Management TimerPCI CLKRUN# and PME# supportSMI# generationAll registers readable/restorable for proper resume from 0 V suspend statesSupport for APM-based legacy power management for non-ACPI Desktop implementations External Glue Integra

25、tionIntegrated Pull-up, Pull-down and Series Termination resistors on IDE, processor I/FIntegrated Pull-down and Series resistors on USB Enhanced DMA ControllerTwo cascaded 8237 DMA controllersSupports LPC DMASMBusNew: Flexible SMBus/SMLink architecture to optimize for ASFProvides independent manage

26、ability bus through SMLink interfaceSupports SMBus 2.0 SpecificationHost interface allows processor to communicate via SMBusSlave interface allows an internal or external Microcontroller to access system resourcesCompatible with most two-wire components that are also I2C compatible High Precision Event TimersAdvanced operating system interrupt scheduling Timers Based on 82C54System timer, Refresh request, Speaker tone output Real-Time Clock256-byte battery-backed CMOS RAMIntegrated oscillator componentsLower Power DC/DC Converter implemen