數(shù)字電路軟件實(shí)驗(yàn)-8學(xué)時(shí)fpga新

§3.3

VHDL的設(shè)計(jì)實(shí)例8位反相器的結(jié)構(gòu)描述ENTITY

inv_8_bit

ISPORT

(x:

IN

STD_LOGIC_VECTOR(1TO

8);y:

OUT

STD_LOGIC_VECTOR(1TO

8);END

inv_8_bit;ARCHITECTURE

struct

OF

inv_8_bit

ISCOMPONENT

invPORT

(i:

IN

STD_LOGIC;o:

OUT

STD_LOGIC);END

COMPONENT;BEGINu:

FOR

n

IN 1

TO

8

GENERATE;v:

inv

FORT

MAP

(x(n),y(n));END

GENERATE;END

struct;元件語句：又稱元件例化就是引入一種連接關(guān)系，可以把以前設(shè)計(jì)好的設(shè)計(jì)實(shí)體定義為一個(gè)元件，然后將此元件與當(dāng)前的設(shè)計(jì)實(shí)體的指定端口相連接，從而為當(dāng)前的設(shè)計(jì)實(shí)體引入一個(gè)新的低一級的設(shè)計(jì)層次。元件定義語句的格式：COMPONENT

元件名

ISPORT（信號名表）；END

COMPONENT;元件調(diào)用語句的格式：例化名：元件名

PORTMAP（信號名表）；生成語句：生成語句用來產(chǎn)生多個(gè)相同的結(jié)構(gòu)，生成語句有一種作用，可

一組完全相同的元件或電路結(jié)構(gòu)。FOR

循環(huán)變量

IN

取值范圍

GENERATE并發(fā)處理語句；END

GENERATE[標(biāo)號]；用半加器和“或門”構(gòu)成全加器。half_adder1half_adder2a

bcinc1

s1scoutc2U2U1half_adderabscLIBRARY

IEEE；USE

IEEE

std_logic_1164.ALL;ENTITY

full_adder

ISPORT

(a，b，cin:

IN

BIT;s,

cout: OUT

BIT);END

full_adder;ARCHITECTURE

arc

OF

full_adder

ISCOMPONENT

half_adderPORT(a,

b:

IN

BIT;s,

c:

OUT

BIT);END

COMPONENT;SIGNAL s1,

c1,

c2:

BIT;BEGINU1:

half_adder

PORT

MAP(a,b,s1,c1);U2:

half_adder

PORT

MAP(s1,cin,s,c2);cout<=

c1

OR

c2;END

arc;三——八譯

的數(shù)據(jù)流描述。LIBRARY

IEEE；USE

IEEE

std_logic_1163.ALL;ENTITY

decoder3_8

ISPORT

(g1，g2a，g2b:

IN

STD_LOGIC;a，b，c：IN

STD_LOGIC;y:

OUT

STD_LOGIC_VECTOR(7DOWNTO

0);END

decoder3_8;ARCHITECTURE

rtl

OF

decoder3_8

ISSIGNAL

comb:

STD_LOGIC_VECTOR(2DOWNTO

0);BEGINcomb

<=

c

&

b

&

a

;PROCESS

(g1，g2a，g2b，comb）BEGINIF(g1=‘1’

AND

g2a=‘0’

AND

g2b=‘0’)

THENCASE

comb

ISWHEN“000”=>y<=“11111110”;WHEN“001”=>y<=“11111101”;WHEN“010”=>y<=“11111011”;WHEN“011”=>y<=“11110111”;WHEN“100”=>y<=“11101111”;WHEN“101”=>y<=“11011111”;WHEN“110”=>y<=“10111111”;WHEN“111”=>y<=“01111111”;WHEN OTHERS

=>y<=“xxxxxxxx”;END

CASE；END

IF；END

PROCESS；END

rtl；三態(tài)輸出“與非”門的性能描述。ENTITY

stm

ISPORT

(i1,

i2,

en:

IN

STD_LOGIC;y:

OUT

STD_LOGIC);END

stm;ARCHITECTURE

behave

OF

stm

ISBEGINPROCESS(i1,

i2,

en)BEGINIF en

=‘1’

THENy<

=

i1

NAND

i2;ELSEY

<=‘Z’;END

IF;END

PROCESS;END

behave;對上述三態(tài)門還可以用條件賦值語句來描述，就得到三態(tài)門的數(shù)據(jù)流描述：ARCHITECTURE

dflow

OF

stm

ISBEGINy<=

i1

NAND

i2

WHEN

(en=“1’)ELSEy

<=

‘Z’;END

dflow;鐘控型觸發(fā)器的描述，上升沿觸發(fā)的D觸發(fā)器。ENTITY

DF

ISPORT

(d,

clk:

IN

BIT;q,qb:

OUT

BIT);END

DF;ARCHITECTURE

behave

OF

DF

ISBEGINPROCESS(clk)BEGINIF(clk

‘

EVENT

AND

clk

=‘1’)

THENq<=

d;qb<=

NOT

d;END

IF;ENDPROCESS;END

behave;帶有異步置位/復(fù)位功能上升沿觸發(fā)的D觸發(fā)器。LIBRARY

IEEE；USE

IEEE.

std_logic

1164.

ALL;ENTITY

dff_2

ISPORT

(d,

clk, s,

r:

IN

STD_LOGIC;q,

qb:

OUT

STD_LOGIC);END

dff_2;ARCHITECTURE

beh

OF

dff_2

ISBEGINBEGINPROCESS(clk,

s,

r)BEGINIF

(s

=

‘0’

AND

r

=‘1’

)

THENq<=‘1

’;qb

<

=‘0’;ELSIF

(

s

=‘1’

AND

r

=‘0’

)

THENq<=‘0

’;qb

<

=‘1’;ELSIF

(

clk’

EVENT

AND clk

=‘1’

)

THENq

<=

d;qb

<=NOT

d;END

IF;END

PROCESS;END

beh;上述語句中就是異步置位/復(fù)位，低有效。設(shè)計(jì)同步復(fù)位上升沿觸發(fā)的D觸發(fā)器。其電路圖如下。QCPdclkclr

1

DqLIBRARY

IEEE；USE

IEEE.

std_logic

1164.

ALL;ENTITY

dff_4

ISPORT

(d,

clk,

clr:

IN

STD_LOGIC;q:

OUT

STD_LOGIC);END

dff_4;ARCHITECTURE

rtl

OF

dff_4

ISBEGINBEGINPROCESS(clk)BEGINIF

(clk’

EVENT

AND clk

=‘1’

)

THENIF

(clr

=

‘1

’)

THENq

<=

‘0’;ELSEq

<=d;END

IF;ENDPROCESS;END

rtl;設(shè)計(jì)一個(gè)分頻器，并通過修改程序中的參數(shù)來實(shí)現(xiàn)不同倍數(shù)的分頻。LIBRARY

IEEE；USE

IEEE.

std_logic

1164.

ALL;USE

IEEE.

std_logic

_UNSIGNED.

ALL;ENTITY

divider_n

ISGENERIC

(n:

INTEGER:=10);PORT

(clki

:

IN

STD_LOGIC;指令：generic

類屬參數(shù)說明；格式：GENERIC（常數(shù)名字表：數(shù)據(jù)類型[：=設(shè)定值]類屬參數(shù)說明是實(shí)體說明組織中的可選項(xiàng)，必須放在端口說明前，用于指定參數(shù)。VHDL中的對象：1、常量；2、變量；3、信號。Signal

信號可以代表電路是實(shí)體動(dòng)態(tài)交換數(shù)據(jù)各元件之間的連接線，段。Signal

信號名：數(shù)據(jù)類型

約束條件：=

表達(dá)式VARIABLE

用于對可變數(shù)據(jù)的臨時(shí)

，變量只能在進(jìn)程語句、函數(shù)語句和過程語句結(jié)構(gòu)中使用，它是一個(gè)局部量。VARIABLE

變量名：數(shù)據(jù)類型

約束條件：=

表達(dá)式clko:

OUT

STD_LOGIC);END

divider_n

；ARCHITECTURE

arc_divider_n

OFdivider_n

ISSIGNAL

qout:

STD_LOGIC;SIGNAL

counter:

INTEGER;BEGINclko<=qout;PROCESS(clki)BEGINIF

(clki’

EVENT

AND clki

=‘1’

)

THENIF

(counter

=

n-1

)

THENqout<=

NOT

qout;counter<=

0;ELSEcounter

<

=

counter

+1;END

IF;END

IF;END

PROCESS;END

arc_divider_n;設(shè)計(jì)一個(gè)十進(jìn)制計(jì)數(shù)器，要求代允許計(jì)數(shù)端和清零端，計(jì)數(shù)允許端和清零端均為高有效，真值表如下。輸入端輸出端clrenclkqdqcqbqa1XX000000X不變不變不變不變01計(jì)數(shù)值加1enclrclkqdqcqbqa十進(jìn)制計(jì)數(shù)器LIBRARY

IEEE；USE

IEEE.

std_logic

1164.

ALL;USE

IEEE.

std_logic

_UNSIGNED.

ALL;ENTITY

count_10

ISPORT

(clk,

clr,

en

:

IN

STD_LOGIC;qa,

qb,

qc,

qd:

OUT

STD_LOGIC);END

count_10;ARCHITECTURE

arc_count10

OF

count_10ISSIGNAL

qout:

STD_LOGIC_VECTOR(3DOWNTO

0);BEGINqa<=qout(0);qb<=qout(1);qc<

=qout(2);qd<=qout(3);PROCESS(clk,

clr)BEGINIF

(clr=‘1’)

THENqout<=

“0000”;ELSIF(clk’

EVENT

AND

clk

=‘1’)

THENIF

(en

=

‘1’)

THENIF

(qout

=“1001”)

THENqout<

=“0000”;ELSEqout<=

qout

+

‘1’;ENDIF;END

IF;END

IF;ENDPROCESS;END

arc_count10;設(shè)計(jì)一個(gè)同步可逆計(jì)數(shù)器，要求代允許計(jì)數(shù)端和清零端，方向控制端，計(jì)數(shù)允許端和清零端均為高有效，真值表如下。輸入端輸出端clrupdownloadclkQ(3)Q(2)Q(1)Q(0)1XXX00000X1X預(yù)置輸入端D狀態(tài)010計(jì)數(shù)值加1000計(jì)數(shù)值減1真值表D(3)D(2)D(1)D(0)clrclkQ(3)Q(2)Q(1)Q(0)十進(jìn)制計(jì)數(shù)器load

updownLIBRARY

IEEE；USE

IEEE.

std_logic

1164.

ALL;USE

IEEE.

std_logic

_UNSIGNED.

ALL;ENTITY

count_4

ISPORT

(clk,

clr,

load,

updown:

INSTD_LOGIC;d:

IN

STD_LOGIC_VECTOR

(3DOWNTO

0));q:

OUT

STD_LOGIC_VECTOR(3DOWNTO

0));END

count_4

；ARCHITECTURE

arc_count4

OF

count_4ISBEGINPROCESS(clk,

clr,

load)BEGINIF

(clr

=‘1’)

THENq

<=

“0000”;ELSIF(load

=

‘1’

)THENq<=dELSIF

(clk‘EVENT

AND

clk

=‘1’)

THENIF

(updown

=‘1’)

THENq

<=

q+1

;ELSEq

<=

q-1

;ENDIF;END

IF;END

PROCESS;END

arc_count4;設(shè)計(jì)一個(gè)moore型狀態(tài)機(jī)。輸出信號僅是現(xiàn)態(tài)的函數(shù)。S0/0S1/1S3/00101S2/01001外輸入輸出LIBRARY

IEEE；USE

IEEE.

std_logic

1164.

ALL;USE

IEEE.

Std_logic

_UNSIGNED.

ALL;ENTITY

moore

ISPORT

(CO,

DIN:

IN

STD_LOGIC;OP: OUT

STD_LOGIC);END

moore;ARCHITECTURE

behave

OF

moore

ISTYPE

STATE

IS (S0,

S1,

S2,

S3);SINGAL

Presentstate

:STATE;SINGAL

Nextstate

:

STATE;BEGINSwitchToNextstate:

Process

(CP)BEGINIF

(CP

‘EVENT

AND

CP

=‘1’)

THEN