FPGA可編程邏輯器件芯片EP2S60F672C5N中文規(guī)格書

1、you need to support configuration input voltages of 1.8 V/1.5 youshould set theVCCSELto a logic high and the Vof the bank thatCCIOcontains the configuration inputs to 1.8 V/1.5 fFor more information on multi-volt support, including information onusingTDO andnCEO in multi-volt systems, refer to theSt

2、ratixIIArchitecturechapter in volume 1 of theStratixII Device Handbook.Configuration SchemesYou can load the configuration data for a device with one of fiveconfiguration schemes (seeTable35), chosen on the basis of the targetapplication. You can use a configuration device, intelligent controller, o

3、rthe JTAG port to configure a StratixII device. A configuration device canautomatically configure a StratixII device at system power-up.You can configure multiple StratixII devices in any of the fiveconfiguration schemes by connecting the configuration enable nCE) andconfiguration enable output nCEO

4、) pins on each device.StratixII FPGAs offer the following:Configuration data decompression to reduce configuration filestorageDesign security using configuration data encryption to protect yourdesignsRemote system upgrades for remotely updating your StratixIIdesignsTable35 summarizes which configura

5、tion features can be used in eachconfiguration scheme.Remote SystemUpgradeDesign Security DecompressionvvvFPPMAX II device or microprocessor andflash device(1)(1)vvEnhanced configuration deviceSerial configuration device(2)vvv(3)vvvvvvvvEnhanced configuration deviceDownload cable(4)Stratix II Device

6、 Handbook, Volume 1ConfigurationRemote SystemUpgradeDesign Security DecompressionMAX II device or microprocessor andflash deviceNotes for Table35:(1) In these modes, the host system must send a DCLK that is 4 the data rate.(2) The enhanced configuration device decompression feature is available, whi

7、le the StratixII decompression featureis not available.(3) Only remote update mode is supported when using the AS configuration scheme. Local update mode is notsupported.(4) The supported download cables include the Altera USB Blaster universal serial bus (USB) port download cable,MasterBlaster seri

8、al/USB communications cable, ByteBlasterII parallel port download cable, and theByteBlasterMV parallel port download cable.Stratix II Device Handbook, Volume 1Configuration &Testing1An encryption configuration file is the same size as a non-encryption configuration file. When using a serial configur

9、ationscheme such as passive serial (PS) or active serial (AS),configuration time is the same whether or not the designsecurity feature is enabled. If the fast passive parallel (FPP)scheme us used with the design security or decompressionfeature, a 4DCLK is required. This results in a slowerconfigura

10、tion time when compared to the configuration time ofan FPGA that has neither the design security, nordecompression feature enabled. For more information aboutthis feature, refer toAN 341: Using the Design Security Feature inStratix II Devices. Contact your local Altera sales representativeto request

11、 this document. Configuration StratixII FPGAs support decompression of configuration data, whichsaves configuration memory space and time. This feature allows you tostore compressed configuration data in configuration devices or othermemory, and transmit this compressed bit stream to StratixIIFPGAs.

12、During configuration, the StratixIIFPGA decompresses the bit stream inreal time and programs its SRAM cells.StratixII FPGAs support decompression in the FPP (when using aMAXII device/microprocessor and flash memory), AS and PSconfiguration schemes. Decompression is not supported in the PPAconfigurat

13、ion scheme nor in JTAG-based configuration. Shortened design cycles, evolving standards, and system deployments inremote locations are difficult challenges faced by modern systemdesigners. StratixII devices can help effectively deal with thesechallenges with their inherent re-programmability and ded

14、icatedcircuitry to perform remote system updates. Remote system updates helpdeliver feature enhancements and bug fixes without costly recalls, reducetime to market, and extend product life.StratixII FPGAs feature dedicated remote system upgrade circuitry tofacilitate remote system updates. Soft logi

15、c s processor or user logic)implemented in the StratixII device can download a new configurationimage from a remote location, store it in configuration memory, and directthe dedicated remote system upgrade circuitry to initiate areconfiguration cycle. The dedicated circuitry performs error detection

16、during and after the configuration process, recovers from any errorcondition by reverting back to a safe configuration image, and providesStratix II Device Handbook, Volume 1Configurationerror status information. This dedicated remote system upgrade circuitryavoids system downtime and is the critica

17、l component for successfulremote system upgrades.RSC is supported in the following StratixII configuration schemes: AS, PS, and PPA. RSC can also be implemented in conjunction withadvanced StratixII features such as real-time decompression ofconfiguration data and design security using AES for secure and efficientfield upgrades.See theRemote System Upgrades With Stratix