2010級(jí)碩士模擬集成電路分析與設(shè)計(jì)期末復(fù)習(xí)題-解答

1、2010級(jí)研究生模擬集成電路分析與設(shè)計(jì)復(fù)習(xí)自己的解答一、Questions：1What is the problem of simple differential circuit? How to solve this problem?Answer: If Vin, CM is low output will be clipped. Solve method: use differential pair.2Describe advantages and drawbacks of differential signals comparing with single-ended signal.Ans

2、wer: Advantages: Higher immunity to environment noise(對(duì)環(huán)境噪聲更具抗干擾能力); Reduce coupled noise in transmission line(減少相鄰信號(hào)線傳輸時(shí)受的干擾); Reject supply noise; Increase output voltage swing; Simpler biasing; Higher linearity Drawbacks: occupy twice areas3. Why analog design needed in Optical Receivers?Answer:

3、High frequency signals are not suitable for transmitting over long distance in the traditional cable due to the severe interference and considerable attenuation because of the limited bandwidth of the cable. In this case, the electrical high frequency signals are converted into the optical signals f

4、irst by the laser diode, then these optic signals are transmitted by an optical fiber, which has extremely wide band and very low loss. In the other end, the optical signals are converted into electrical signals again by the photodiode.書(shū)(中)P3；（英）P44. Which two figures play most important role in tec

5、hnology nodes scaling down? Please describe in detail.Answer: Minimum channel length often represents the technology nodes. Oxide thickness often affects the threshold voltage and the power supply.5. If there is a small mismatch between M1 and M2, how do the parameters of the transistors affect the

6、common mode rejection ratio (CMRR) of a differential pair?(中)P1016. Write the input pole of the circuit in Fig. 1.Answer: The input pole: win=1/RS (1+A)CF7. When both NMOS and PMOS devices are needed to be placed on one chip, what is needed?Answer: N-Well or P-Well is needed.8. What is the problem f

7、or the circuit in Fig. 2? Any suggestions to solve it?Answer: Small-signal drain current of M1 is “wasted”. Solve method: Use differential pair with active current mirror to combine the small-signal current together.9. Among the output noise and the input-referred noise, which one is more popular to

8、 be used in the circuit simulation? Why?Answer: Since the output noise depends on the gain, it is hard to fairly compare the effects of noise of different circuits because of the different gain. Therefore, the input-referred noise is more popular to be used in the circuit simulation.10. Refer to Fig

9、. 3, what benefits do we have for using cascode structure in current source? And any drawbacks?Answer: Advantages: Largely reduce the change so that VY is more close to VX, and hence Iout more closely track IREF. Drawbacks: Cost higher voltage headroom.Fig.1Fig. 3Fig. 211. Can we use the statistical

10、 value of noise amplititude ? If the answer is no, then what we usually use when considering the noise in circuit systems? Explain the reason. Answer: No. Because the statistical value of noise amplitude over time domain is zero. Fortunately the statistical value of power overall time domain is not

11、zero. So we usually incorporate average power of a random signal in circuit analysis.12. Explain why use diode-connected for M1 in Fig. 4Answer: Diode-connected to ensure M1 always in saturation.13. Describe the steps for calculating the loop gain of a feedback system. And calculate LG in Fig. 5 fol

12、lowing the steps.Answer: Step 1: Set the main input to zero; Step 2: Break the loop at some point; Step 3: Inject a test signal in the “right direction”; Step 4: Follow the signal around the loop; Step 5: Obtain the value that returns to the break point; Step 6: The negative of the transfer function

13、 derived is the loop gain;14. What is CMRR? Write down the definition of it.Answer: Common mode rejection ratio (共模抑制比）: Where gm denotes the mean value: gm=(gm1+gm2)/215. Write the input and output pole of the circuit in Fig. 6, ignoring the effect of CGs and RS on Cout.Answer: Low frequency gain:

14、Using Miller Theorem: Therefore, the input pole is: If not consider the effect of Rs and CGS on Cout, Using Miller Theorem again: The output pole can be written as: 16. Plot a diagram of a simple PLL and explain the working principle of it in short.Answer: Phase detector (PD) compares the phases of

15、Vout and Vin, generating an error signal;Low-pass filter (LPF) transfer the error wave to a dc level to the oscillator;The dc level can control the output frequency by VCO;In this way, the frequency and phase of Vout can be locked to Vin.17. What is Power spectral density (PSD)? Use the expression a

16、nd the plot to show it.Answer:（書(shū)）表示在每個(gè)頻率上信號(hào)具有的功率大小。更確切的說(shuō)，噪聲波形x(t)的PSD，即SX(f)，被定義為f附近1Hz帶寬內(nèi)x(t)具有的平均功率。Power spectral density (PSD): the spectrum shows how much power the signal carries at each frequency, written as Sx(f). 18. How do the best references should be?Answer: Independent on supply; Indepe

17、ndent on temperature.19. Describe the applications of PLLs.Answer: Frequency Multiplication (頻率倍增）；Frequency Synthesis （頻率合成） Skew reduction （偏移的減?。籎itter reduction（抖動(dòng)的減?。?0. For simplify calculations, in reality, how is the average noise power (Pav) is defined? In this case, how to express the act

18、ual power and root-mean-square (rms) voltage for nose?Answer: For simplify calculations, in reality, Pav is defined as: And then the actual power and root-mean-square (rms) voltage for nose becomes as:21. What is the white spectrum? Use the plot to show it.Answer: PSD is same at all frequencies, sim

19、ilar to white light. 22. Describe the stable condition of a feedback system.Answer: When |bH(w1)| 1, always keeps -180o (can also say that phase shift 180o); Or when bH(w1) -180o, always keeps |bH(w1)| 1.23. Explain briefly the oscillating principle of the three-stage CMOS converters.Answer: noise w

20、ill disturb this balance, yielding oscillating at frequency of , when amplitude grows and the circuit becomes nonlinear, the oscillation frequency shifts to 1/(6TD).Fig. 6Fig. 4Fig.5二、Calculations (Device parameters refer to table 2.1)1. Assuming symmetry and all of the transistors in the circuit of

21、 Fig.7 are saturated and l 0, calculate the small-signal differential voltage gain of the circuit. 2Design the folded-cascode op amp of Fig. 8 for the following requirements: maximum differential swing = 2.4 V, total power dissipation = 6 mW. If all of the transistors have a channel length of 0.5 mm, what is the overall voltage gain? Can the input common-mode level be as low as zero? 3. Consider the common-source stage of Fig. 9. Ignore the flicker noise, assume (W/L)1=50/0.5, ID1=ID2=0.1 mA, and VDD=3 V. If the contribution of M2 to the input-referred noise voltage (not voltage squared