電子信息工程基于VHDL的100進(jìn)制計(jì)數(shù)器報(bào)告

1、可編程邏輯器件應(yīng)用項(xiàng)目報(bào)告書項(xiàng)目名稱：100進(jìn)制計(jì)數(shù)器指導(dǎo)老師：龔蘭芳姓名:李詩(shī)華學(xué)號(hào):080212215班級(jí)：08電子2班廣東水利電力職業(yè)技術(shù)學(xué)院目錄一、設(shè)計(jì)要求二、設(shè)計(jì)目的二、設(shè)計(jì)方案四、設(shè)計(jì)原理五、硬件要求六、調(diào)試與問題疑點(diǎn)七、設(shè)計(jì)步驟 八、體會(huì)、對(duì)設(shè)計(jì)工作的總結(jié)與展望、設(shè)計(jì)要求(1) 設(shè)計(jì)帶計(jì)數(shù)允許和復(fù)位輸入的100進(jìn)制計(jì)數(shù)器，要求完成頂層 電路圖和底層VHDL文件；(2) 進(jìn)行功能仿真；(3) 下載并驗(yàn)證計(jì)數(shù)器功能；(4) 按上述步驟設(shè)計(jì)100進(jìn)制計(jì)數(shù)器；(5) 為上述設(shè)計(jì)建立元件符號(hào)。、設(shè)計(jì)目的(1) 設(shè)計(jì)一個(gè)帶計(jì)數(shù)允許和復(fù)位端的100進(jìn)制計(jì)數(shù)器。(2) 熟練掌握各種計(jì)數(shù)器類型模塊

2、的描述方法。(3) 能用計(jì)數(shù)器構(gòu)成十進(jìn)制、六十進(jìn)制、十二進(jìn)制等所需進(jìn)制的計(jì) 數(shù)器。(4) 體會(huì)EDA技術(shù)的優(yōu)點(diǎn)。設(shè)計(jì)兩個(gè)按鍵，一個(gè)有停止、開始的功能，另一個(gè)有復(fù)位清零的功能，具體的 看表1-1。表1-1按鍵狀態(tài)功能EnEn=1f開始計(jì)時(shí)En=0停止計(jì)時(shí)RstRst=0復(fù)位清零通過(guò)分頻分出1KHZ對(duì)數(shù)碼管的位地址進(jìn)行掃描，而100KHZ利用if-else設(shè)計(jì) 計(jì)數(shù)程序，并輸出顯示信號(hào)。利用多個(gè)進(jìn)程來(lái)完成以上的設(shè)計(jì)方案。四、設(shè)計(jì)原理library ieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_l

3、ogic_arith.all;entity bcd_100d isport(en,rst,clk:in std_logic;duan:out std_logic_vector(5 downto 0); cout:out std_logic_vector(6 downto 0);end;architecture one of bcd_100d issignal clk_1k:std_logic;signal clk_100h:std_logic;signal cnt6:integer range 0 to 3;signal data:std_logic_vector(3 downto 0);si

4、gnal data1:std_logic_vector(3 downto 0);signal dout:std_logic_vector(5 downto 0);signal s:std_logic_vector(6 downto 0);signal led1,led2,led3,led4:std_logic_vector(3 downto 0);beginprocess (clk)variable cnt1:integer range 0 to 250;variable cnt2:integer range 0 to 100;beginif clk'event and clk=

5、9;1' thenif cnt1=250 then cnt1:=0;if cnt2=100 then cnt2:=0;clk_1k<=not clk_1k;elsecnt2:=cnt2+1;end if;elsecnt1:=cnt1+1;end if;end if;end process;process (clk)variable cnt1:integer range 0 to 4000;variable cnt2:integer range 0 to 4000;beginif clk'event and clk='1' then if cnt1=4000

6、 thencnt1:=0;if cnt2=4000 thencnt2:=0; clk_100h<=not clk_100h;elsecnt2:=cnt2+1;end if;elsecnt1:=cnt1+1;end if;end if;end process;process(clk_1k)beginif clk_1k'event and clk_1k='1' then if cnt6=3 thencnt6<=0;elsecnt6<=cnt6+1;end if;end if;end process;process(cnt6)begincase cnt6 i

7、swhen 0=>dout<="111110"when 1=>dout<="111101"when others=>null;end case;end process;process(dout)begincase dout iswhen"111110"=>data<=led1;when"111101"=>data<=led2; when others=>null;end case;end process;process(clk_100h) beginif

8、rst='0' thenled2<="0000"led1<="0000"elsif clk_100h'event and clk_100h='1' thenif en='1' thencase led1 iswhen"1001"=> led1<="0000"case led2 iswhen"1001"=>led2<="0000"led1<="0000"when

9、 others=>led2<=led2+1;end case;when others=>led1<=led1+1;end case;end if;end if;end process;process(data)begincase data iswhen"0000"=>s<="0111111"-0when"0001"=>s<="0000110"-1when"0010"=>s<="1011011"-2when"

10、0011"=>s<="1001111"-3when"0100"=>s<="1100110"-4when"0101"=>s<="1101101"-5when"0110"=>s<="1111101"-6when"0111"=>s<="0000111"-7when"1000"=>s<="1111111"

11、-8when"1001"=>s<="1101111"-9 when others=>null;end case;end process;duan<=dout;cout<=s;end;五、硬件要求表2-1六、調(diào)試與問題疑點(diǎn) 問題疑點(diǎn)：1. 怎樣實(shí)現(xiàn)兩數(shù)碼管同時(shí)顯示.2. 怎樣實(shí)現(xiàn)數(shù)字的循環(huán).調(diào)試：1. 編譯無(wú)誤，然后就對(duì)照自己所設(shè)計(jì)的功能按鍵狀態(tài)（表1-1）,看是否符合設(shè)計(jì)結(jié)果要求2. 檢查無(wú)誤，然后對(duì)自己規(guī)定的設(shè)計(jì)方案分配引腳（表2-1）,進(jìn)行編譯無(wú)誤， 就下載到實(shí)驗(yàn)板上來(lái)驗(yàn)證設(shè)計(jì)效果如果與自己的想法有出入，就要進(jìn)行 修改最后要達(dá)到自己的結(jié)果.3. 驗(yàn)證的結(jié)果與是否符合自己所規(guī)定的設(shè)計(jì)方案.七、設(shè)計(jì)步驟 輸出位選信號(hào)八、體會(huì)、對(duì)設(shè)計(jì)工作的總結(jié)與展望分頻進(jìn)程100HZ計(jì)數(shù)進(jìn)程輸出數(shù)碼管段碼信號(hào)顯示進(jìn)程在這次設(shè)計(jì)實(shí)驗(yàn)中，我深刻地