數(shù)字電路設(shè)計課件第四講VHDL的基本功能描述語句

1、數(shù)字電路設(shè)計課件第四數(shù)字電路設(shè)計課件第四講講VHDLVHDL的根本功能描述的根本功能描述語句語句BeginEnd進程進程1進程進程2A = “0011”When-ElseArchitectureBeginEnd進程進程1進程進程2A = “0011”When-ElseArchitecturel直接信號賦值語句直接信號賦值語句l條件信號賦值語句條件信號賦值語句l選擇信號賦值語句選擇信號賦值語句邏輯表達(dá)式邏輯表達(dá)式ABCDEABCDEj = j = w when (a = 1) elsew when (a = 1) else x when (b = 1) elsex when (b = 1) el

2、se y when (c = 1) elsey when (c = 1) elsez when (d = 1) elsez when (d = 1) else0 ;0 ;WITHWITH selection_signal selection_signal SELECTSELECT signal_name signal_name = value_1 value_1 WHENWHEN value_a value_a, , value_2 value_2 WHENWHEN value_b value_b, , . value_n value_n WHENWHEN value_n value_n, ,

3、 value_x value_x WHEN OTHERS;WHEN OTHERS;l每個每個WHEN子句可以包含多個條件子句可以包含多個條件:LIBRARY ieee;USEENTITY if_case IS PORT( a, b, c, d : IN Std_Logic;sel : IN Std_Logic_Vector(1 downto 0); y, z : OUT Std_Logic);END if_case;ARCHITECTURE logic OF if_case ISBEGINif_label: PROCESS(a, b, c, d, sel)BEGINIF sel=00 THEN

4、 y = a;ELSIF sel=01 THEN y = b;ELSIF sel=10 THEN y = c;ELSE y z z z z z = 0;END CASE;END PROCESS case_label;END logic;都列入敏感表中都列入敏感表中aoeyARCHITECTURE reg1 OF reg1 ISSIGNAL a, b : BIT;BEGINPROCESS (clk)BEGINIF clkevent and clk=1 THENa = d;b = a;q = b;END IF;END PROCESS;END reg1;ENTITY reg1 IS PORT ( d

5、, clk : in BIT; q : out BIT);END reg1;ARCHITECTURE reg1 OF reg1 ISSIGNAL a, b : BIT;BEGINPROCESS (clk)BEGINIF clkevent and clk=1 THENa = d;b = a;END IF;END PROCESS;q = b;END reg1;ENTITY reg1 IS PORT ( d, clk : in BIT; q : out BIT);END reg1;ARCHITECTURE reg1 OF reg1 ISBEGINPROCESS (clk)VARIABLE a, b

6、: BIT;BEGINIF clkevent and clk=1 THENa := d;b := a;q = b;END IF;END PROCESS;END reg1;l變量在IF語句中被賦值，以用來表示隨時鐘的變化，不會產(chǎn)生觸發(fā)器l變量只代表臨時存儲，不反映實際硬件l變量可用在表示一數(shù)據(jù)立即變化的表達(dá)式中，然后再將變量的值賦給信號rising_edge(clok)選擇信號選擇信號不同選擇值不同選擇值不同流向不同流向模式模式1： LOOP標(biāo)號標(biāo)號: LOOP 順序語句順序語句 EXIT LOOP標(biāo)號標(biāo)號 ; END LOOP;模式模式2： WHILE LOOP 順序語句順序語句END LOO

7、P;模式模式3： FOR IN LOOP順序語句順序語句END LOOP;LIBRARY ieee;USEUSEENTITY shift4 ISPORT ( shft_lft : in std_logic;d_in : in std_logic_vector(3 downto 0);q_out: out std_logic_vector(7 downto 0);END shift4;ARCHITECTURE logic OF shift4 ISBEGINPROCESS(d_in, shft_lft)VARIABLE shft_var : std_logic_vector(7 DOWNTO 0);BEGINshft_var(7 downto 4) := 0000;shft_var(3 downto 0) := d_in;IF shft_lft = 1 THENFOR i IN 7 DOWNTO 4 LOOPshft_var(i) := shft_var(i-4);END LOOP;shft_var(3 d