進制同步計數(shù)器設計報告.docx

1、浙江萬里學院實驗報告成績：課程名稱：可編程邏輯器件應用教師：施炯實驗名稱： 100 進制同步計數(shù)器設計專業(yè)班級：電子103 姓名：徐強學號： 2018014092 實驗日期： 2018.5.10一、實驗目的：1、掌握計數(shù)器的原理及設計方法；2、設計一個 0100的計數(shù)器；3、利用實驗二的七段數(shù)碼管電路進行顯示；二、實驗要求：1、用 VHDL 語言進行描寫；2、有計數(shù)顯示輸出；3、有清零端和計數(shù)使能端；三、實驗結果：1. VHDL 程序LIBRARY IEEE 。USE IEEE.STD_LOGIC_1164.ALL 。PACKAGE my_pkg ISComponent nd2-或門PORT

2、(a,b: IN STD_LOGIC。c: OUT STD_LOGIC 。END Component。Component led_decoderPORT (din:in std_logic_vector(3 downto 0 。 -四位二進制碼輸入 seg:out std_logic_vector(6 downto 0 。 -輸出 LED 七段碼END Component。Component CNT60 -2 位 BCD 碼 60 進制計數(shù)器PORT(CR:IN STD_LOGIC 。EN:IN STD_LOGIC 。CLK:IN STD_LOGIC 。OUTLOW:BUFFER STD_LO

3、GIC_VECTOR(3 DOWNTO 0 。OUTHIGH:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0。END Component。Component CNT100 -帶使能和清零信號的100 進制計數(shù)器PORT(CLK:IN STD_LOGIC 。EN:IN STD_LOGIC 。CLR:IN STD_LOGIC 。OUTLOW:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0 。OUTHIGH:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0。END Component。Component freq_div-50MHZ 時

4、鐘分頻出 1HzPORT(clkinput : IN STD_LOGIC 。output : OUT STD_LOGIC。END Component。2 / 8Component jtd-交通燈控制器PORT(CLKIN:IN STD_LOGIC 。-50MHZR1,G1,R2,G2,R3,G3,R4,G4:OUT STD_LOGIC。 -紅綠燈信號輸出 GAO,DI:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0 - 倒計時輸出。END Component。END my_pkg。LIBRARY IEEE 。USE IEEE.STD_LOGIC_1164.ALL 。USE

5、 work.my_pkg.ALL 。-打開程序包ENTITY Demo3 ISPORT (CRl:IN STD_LOGIC 。ENl:IN STD_LOGIC 。CLKIN: IN STD_LOGIC 。LEDLOW,LEDHIGH: OUT STD_LOGIC_VECTOR(6 downto 0。END Demo3。ARCHITECTURE behv OF Demo3 ISSIGNAL CLKTEMP: STD_LOGIC 。-定義中轉信號SIGNAL LEDLOWTEMP,LEDHIGHTEMP:STD_LOGIC_VECTOR(3 downto 0。BEGINu1:freq_div PO

6、RT MAP(CLKIN,CLKTEMP 。-位置關聯(lián)方式u2:CNT60 PORTMAP(CR=CRl,EN=ENl,CLK=CLKTEMP,OUTLOW=LEDLOWTEMP,OUTHIGH=LEDHIGHTEMP。-名字關聯(lián)方式3 / 8u3:led_decoder PORT MAP(LEDLOWTEMP,LEDLOW 。-低位數(shù)碼管輸出u4:led_decoder PORT MAP(LEDHIGHTEMP,LEDHIGH 。-高位數(shù)碼管輸出END behv。LIBRARY ieee 。USE ieee.std_logic_1164.all。ENTITY freq_div ISPORT(

7、clkinput : IN STD_LOGIC 。output : OUT STD_LOGIC。END freq_div 。ARCHITECTURE rt OF freq_div ISSIGNAL count_signal : INTEGERRANGE 0 TO 25000000 。signal mid1 : STD_LOGIC 。BEGINPROCESS (clkinputBEGINIF (clkinputEVENT AND clkinput = 1 THENif count_signal=24999999 then -50MHz division to 1Hz count_signal =

8、 0。mid1= not mid1。elsecount_signal = count_signal + 1。4 / 8end if。output 。 -四位二進制碼輸入 seg:out std_logic_vector(6 downto 0 。 -輸出 LED 七段碼end led_decoder。architecture Behavioral of led_decoder isbeginprocess(dinbegincase din iswhen 0000 =seg seg seg seg seg seg seg seg seg seg seg 。OUTHIGH:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0。END CNT60 。ARCHITECTURE behav OF CNT60 ISBEGINPROCESS(CLK,CR,ENBEGINif CR=1 thenOUTHIGH=0000 。OUTLOW=0000 。elsif EN =1thenIF CLKEVENT AND CLK=1 THEN6 / 8IF OUTHIGH=1001 AND OUTLOW=1001 THENOUTHIGH=0000 。OUTLOW=0000 。ELSIF OUTLOW=1001 THENOU