guoqian視頻2 參考資料 芯片資料 arm arm-manual qrc_thumbside

1、Vector Floating Point Quick Reference Cardtruction SetIf Fd is S0-S7 or D0-D3, operation is Scalar (regardless of vector length).If Fd is S8-S31 or D4-D15, and Fm is S0-S7 or D0-D3, operation is Mixed (Fm scalar, others vector).If Fd is S8-S31 or D4-D15, and Fm is S8-S31 or D4-D15, operation is Vect

2、or.S0-S7 (or D0-D3), S8-S15 (D4-D7), S16-S23 (D8-D11), S24-S31 (D12-D15) each form a circulating bank of registers.FPSCR formatRounding(Stride 1)*3Vector length 1Exception trap enable bitsCumulative exception bits3130292824232221201817161211109843210NZCVFZRMODESTRIDELENIXEUFEOFEDZEIOEIXCUFCOFCDZCIOC

3、FZ: 1 = flush to zero mode.Rounding: 0 = round to nearest, 1 = towards +, 2 = towards , 3 = towards zero.(Vector length * Stride) must not exceed 4 for double precisionoperands.OperationAssemblerExceptionsActionNotesVector arithmeticMultiplyand negateand accumulate negate and accumulate and subtract

4、negate and subtract AddSubtract Divide Copy Absolute Negative Square rootFMULcond Fd, Fn, Fm FNMULcond Fd, Fn, Fm FMACcond Fd, Fn, Fm FNMACcond Fd, Fn, Fm FMSCcond Fd, Fn, Fm FNMSCcond Fd, Fn, Fm FADDcond Fd, Fn, Fm FSUBcond Fd, Fn, Fm FDIVcond Fd, Fn, Fm FCPYcond Fd, Fm FABScond Fd, Fm FNEGcond Fd,

5、 Fm FSQRTcond Fd, FmIO, OF, UF, IX IO, OF, UF, IX IO, OF, UF, IX IO, OF, UF, IX IO, OF, UF, IX IO, OF, UF, IX IO, OF, IXIO, OF, IXIO, DZ, OF, UF, IXIO, IXFd := Fn * FmFd := (Fn * Fm)Fd := Fd + (Fn * Fm) Fd := Fd (Fn * Fm) Fd := Fd + (Fn * Fm) Fd := Fd (Fn * Fm) Fd := Fn + FmFd := Fn Fm Fd := Fn / Fm

6、 Fd := FmFd := abs(Fm) Fd := FmFd := sqrt(Fm)Scalar compare Scalar convertCompare with zero Single to double Double to singleUnsigned integer to float Signed integer to float Float to unsigned integer Float to signed integerFCMPEcond Fd, Fm FCMPEZcond FdFCVTDScond Dd, Sm FCVTSDcond Sd, Dm FUITOcond

7、Fd, Sm FSITOcond Fd, Sm FTOUIZcond Sd, Fm FTOSIZcond Sd, FmIO IO IOIO, OF, UF, IX IXIX IO, IX IO, IXSet FPSCR flags on Fd Fm Set FPSCR flags on Fd 0 Dd := convertStoD(Sm)Sd := convertDtoS(Dm) Fd := convertUItoF(Sm) Fd := convertSItoF(Sm) Sd := convertFtoUI(Fm) Sd := convertFtoSI(Fm)Use FMSTAT to tra

8、nsfer flags. Use FMSTAT to transfer flags.Save VFP registersLoad VFP registersMultiple, unindexed increment after decrement beforeMultiple, unindexed increment after decrement beforeFSTcond Fd, Rn, # FSTMIAcond Rn, FSTMIAcond Rn!, FSTMDBcond Rn!, FLDcond Fd, Rn, # FLDMIAcond Rn, FLDMIAcond Rn!, FLDM

9、DBcond Rn!, address := FdSaves list of VFP registers, starting at address in Rn. synonym: FSTMEA (empty ascending) synonym: FSTMFD (full descending)Fd := addressLoads list of VFP registers, starting at address in Rn. synonym: FLDMFD (full descending)synonym: FLDMEA (empty ascending)Transfer register

10、sARM to single Single to ARMARM to lower half of double Lower half of double to ARM ARM to upper half of double Upper half of double to ARM ARM to VFP system register VFP system register to ARM FPSCR flags to CPSRFMSRcond Sn, Rd FMRScond Rd, Sn FMDLRcond Dn, Rd FMRDLcond Rd, Dn FMDHRcond Dn, Rd FMRD

11、Hcond Rd, Dn FMXRcond , Rd FMRXcond Rd, FMSTATcondSn := Rd Rd := SnDn31:0 := RdRd := Dn31:0Dn63:32 := RdRd := Dn63:32VFPsysreg := Rd Rd := VFPsysregCPSR flags := FPSCR flagsUse with FMDHR. Use with FMRDH. Use with FMDLR. Use with FMRDL.Stalls ARM until all VFP ops complete. Stalls ARM until all VFP

12、ops complete. Equivalent to FMRX R15, FPSCRExceptionsIO OF UF IX DZInvalid operation Overflow Underflow Inexact result Division by zeroEZE : raise exception on any NaN. Without E : raise exception only on signaling NaNs. Round towards zero. Overrides FPSCR rounding mode.A comma separated list of con

13、secutive VFP registers, enclosed in braces ( and ). FPSCR, or FPSID.Key to TablescondFd, Fn, FmSee Table Condition Field (on ARM side). S (single precision) or D (double precision). As above, or X (unspecified precision).Sd, Sn, Sm (single precision), or Dd, Dn, Dm (double precision).Thumbtruction S

14、etQuick Reference CardOperationAssemblerUpdatesActionNotesMoveImmediate Lo to LoHi to Lo, Lo to Hi, Hi to HiMOV Rd, # MOV Rd, RmMOV Rd, RmN ZN Z * *Rd := immed_8 Rd := RmRd := Rm8-bit immediate value.* Clears C and V flags.Not Lo to Lo. Flags not affected.ArithmeticAddLo and LoHi to Lo, Lo to Hi, Hi

15、 to Hi immediatewith carry value to SPform address from SP form address from PCSubtractimmediate 3immediate 8 with carry value from SPNegate Multiply Comparenegative immediateNo operationADD Rd, Rn, # ADD Rd, Rn, RmADD Rd, RmADD Rd, # ADC Rd, RmADD SP, # ADD Rd, SP, # ADD Rd, PC, # SUB Rd, Rn, RmSUB

16、 Rd, Rn, # SUB Rd, # SBC Rd, RmSUB SP, # NEG Rd, RmMUL Rd, Rm CMP Rn, Rm CMN Rn, RmCMP Rn, # NOPN Z C V N Z C VN Z C V N Z C VN Z C V N Z C V N Z C V N Z C VN Z C VN Z * * N Z C V N Z C V N Z C VRd := Rn + immed_3 Rd := Rn + RmRd := Rd + RmRd := Rd + immed_8 Rd := Rd + Rm + C-bitR13 := R13 + immed_7

17、 * 4 Rd := R13 + immed_8 * 4Rd := (R15 AND 0xFFFFFFFC) + immed_8 * 4Rd := Rn RmRd := Rn immed_3 Rd := Rd immed_8Rd := Rd Rm NOT C-bit R13 := R13 immed_7 * 4 Rd := RmRd := Rm * Rdupdate CPSR flags on Rn Rm update CPSR flags on Rn + Rm update CPSR flags on Rn immed_8 R8 := R83-bit immediate value.Not

18、Lo to Lo. Flags not affected. 8-bit immediate value.9-bit immediate value (word-aligned). Flags not affected. 10-bit immediate value (word-aligned). Flags not affected. 10-bit immediate value (word-aligned). Flags not affected.3-bit immediate value. 8-bit immediate value.9-bit immediate value (word-

19、aligned). Flags not affected.* C and V flags unpredictable in 4T, unchanged in 5T. Can be Lo to Lo, Lo to Hi, Hi to Lo, or Hi to Hi.8-bit immediate value. Flags not affected.LogicalANDExclusive OR ORBit clear Move NOT Test bitsAND Rd, Rm EOR Rd, Rm ORR Rd, Rm BIC Rd, Rm MVN Rd, Rm TST Rn, RmN ZN ZN

20、ZN ZN ZN ZRd := Rd AND Rm Rd := Rd EOR Rm Rd := Rd OR RmRd := Rd AND NOT Rm Rd := NOT Rmupdate CPSR flags on Rn AND RmShift/rotateLogical shift left Logical shift right Arithmetic shift rightRotate rightLSL Rd, Rm, # LSL Rd, RsLSR Rd, Rm, # LSR Rd, RsASR Rd, Rm, # ASR Rd, RsROR Rd, RsN Z C* N Z C* N

21、 Z C N Z C N Z C N Z C* N Z C*Rd := Rm immed_5 Rd := Rd immed_5 Rd := Rd Rs7:0Rd := Rm ASR immed_5 Rd := Rd ASR Rs7:0 Rd := Rd ROR Rs7:0Allowed shifts 0-31. * C flag unaffected if shift is 0.* C flag unaffected if Rs7:0 is 0. Allowed shifts 1-32.* C flag unaffected if Rs7:0 is 0. Allowed shifts 1-32

22、.* C flag unaffected if Rs7:0 is 0.* C flag unaffected if Rs7:0 is 0.BranchConditional branchUnconditional branch Long branch with linkBranch and exchangeBranch with link and exchange Branch with link and exchange5T5TBcond labelB label BL labelBX RmBLX label BLX RmR15 := labelR15 := labelR14 := R15

23、2, R15 := labelR15 := Rm AND 0xFFFFFFFE R14 := R15 2, R15 := labelChange to ARMR14 := R15 2, R15 := Rm AND 0xFFFFFFFEChange to ARM if Rm0 = 0label must be within 252 to + 258 bytes of current truction. See Table Condition Field (ARM side). AL not allowed.label must be within 2Kb of current truction.

24、 Encoded as two Thumbtructions.label must be within 4Mb of current truction.Change to ARM state if Rm0 = 0. Encoded as two Thumbtructions.label must be within 4Mb of current truction.Software InterruptSWI Software interrupt processor exception8-bit immediate value encoded in truction.Breakpoint5TBKP

25、T Prefetch abort or enter debug stateAll Thumb registers are Lo (R0-R7) except where specified. Hi registers are R8-R15.Thumbtruction SetQuick Reference CardProprietary NoticeWords and logos marked with or are registered trademarks or trademarks owned by ARM Limited. Other brands and names mentioned

26、 herein may be the trademarks of their respective owners.Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.The product described

27、 in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness

28、for purpose, are excluded.This reference card is intended only to assist the reader in the use of the product. ARM Ltd shall not be liable for any loss or damage arising from the use of any information in this reference card, or any error or omission uch information, or any incorrect use of the prod

29、uct.Document NumberARM QRC 0001EChange LogIssueA B C D EDateJune 1995Sept 1996Nov 1998Oct 1999Oct 2000ChangeFirst Release Second Release Third Release Fourth Release Fifth ReleaseBy BJH BJH BJH CKS CKSOperationAssemblerActionNotesLoadwith immediate offset, word halfwordbytewith register o

30、ffset, word halfwordsigned halfword bytesigned byte PC-relativeSP-relative MultipleLDR Rd, Rn, # LDRH Rd, Rn, # LDRB Rd, Rn, # LDR Rd, Rn, RmLDRH Rd, Rn, Rm LDRSH Rd, Rn, Rm LDRB Rd, Rn, Rm LDRSB Rd, Rn, RmLDR Rd, PC, # LDR Rd, SP, # LDMIA Rn!, Rd := Rn + immed_5 * 4Rd := ZeroExtend(Rn + immed_5 * 215:0) Rd := ZeroExtend(Rn + immed_57:0)Rd := Rn + RmRd := ZeroExtend(Rn + Rm15:0) Rd := SignExtend(Rn + Rm15:0) Rd := ZeroExtend(Rn + Rm7:0) Rd := SignExtend(Rn + Rm7:0)R