AHDL語(yǔ)言介紹ppt課件

1、AHDL訓(xùn)練教程,哈爾濱工業(yè)大學(xué)威海校區(qū) 戴伏生,什么是 AHDL,Altera Hardware Description Language 由 Altera公司開(kāi)發(fā) 集成到Altera的軟件 Max+Plus II 用語(yǔ)言描述硬件來(lái)代替圖形 修改更容易 易于維護(hù) 非常適合于 復(fù)雜的組合邏輯 BCD 到 7段轉(zhuǎn)換 地址解碼 狀態(tài)機(jī) 其他你想要的.,繼續(xù).,就象圖形輸入一樣容易 強(qiáng)有力的HDL (硬件描述語(yǔ)言) VHDL, Verilog HDL 等等.,怎樣用ADHL,用任何文本編輯器建立這個(gè)文件 Altera 軟件 Max+Plus II 提供文本編輯器,輸入你的 AHDL 設(shè)計(jì)文件,繼續(xù).

2、,用 name.TDF保存你的ADHL文件,繼續(xù).,編譯期間的錯(cuò)誤定位,方便的錯(cuò)誤定位,通常的AHDL格式,SUBDESIGN decode1 ( input_pin_name : INPUT; input_bus_name15.0 : INPUT; output_pin_name : OUTPUT; output_bus_name : OUTPUT; ) BEGIN ouptut_pin_name = input_pin_name; output_bus_name = input_bus_name; END;,關(guān)鍵字,定義I/O口,邏輯,AHDL 格式,你的第一個(gè)AHDL設(shè)計(jì) 地址解碼器,C

3、hip_enable = a0 chip_enable : output; ) begin chip_enable = (a3.0 = H7); end;,為什么我用AHDL代替圖形,容易編輯 Document during the coding 我想解碼 H”A” 不是 H”7”,SUBDESIGN decode1 ( a3.0 : input; chip_enable : output; ) begin chip_enable = (a3.0 = HA); end;,Self Explain the Function,唯一的改動(dòng),需要更多的工作去修改,Chip_enable = !a0 c

4、hip_enable : output; ) begin chip_enable = (a3.0 = B1x0 x); end;,一些無(wú)關(guān)位寫(xiě)X忽略,需要你知道的一些事情,加 : + 減 : - 數(shù)字恒等 : = 不等于 : != 大于 : 大于或等于 : = 小于 : 小于或等于 : = 邏輯或 : # 邏輯與 : SUBDESIGN decode1 ( a3.0 : input; chip_enable : output; ) begin chip_enable = (a3.0 = IO_ADDRESS); if (a3.0 = IO_ADDRESS) then . end;,在 SUBD

5、ESIGN 關(guān)鍵字之前定義 CONSTANT,實(shí)現(xiàn)組合邏輯,out1 = a0 out3.0 : output; ) begin out0 = a0 ,總線操作的更多內(nèi)容,總線操作 a9.0, b9.0 a = b; a7.4 = b9.6; a9.8 = VCC; a9.8 = 1; a9.8 = 2; a9.8 = 3; a3.0 = GND a3.0 = 0; temp = b0 a2.1 = temp,a7=b9, a6=b8, a5=b7, a4=b6,a9.8 connect to VCC,a9.8 = B”01”,a9.8 = B”10”,a9.8 = B”11”,a3.0 co

6、nnect to GND,a3.0 = B”0000”,a2 = temp, a1 = temp,高級(jí)總線操作,總線Bus b3.0 b3, b2, b1, b0 (有四個(gè)成員) MSB 是 b3, LSB 是b0 陣列ARRAY BUS a3.02.0 a3_2, a3_1, a3_0, a2_2, a2_1, a2_0, a1_2, a1_1, a1_0, a0_2, a0_1, a0_0 (有12個(gè)成員） MSB 是 a3_2, LSB 是 a0_0,真值表,i3.0 Segment 7 0 0 1 1 2 2 F F,做任何改動(dòng)都很容易,IF-THEN-ELSE,SUBDESIGN p

7、riority ( low, medium, high : input; highest_level3.0 : output; ) begin if ( high = B”1”) then highest_level = B”1000”; elsif (medium = B”1”) then highest_level = B”0100”; elsif (low = B”1”) then highest_level = B”0010”; else highest_level = B”0001”; end if; end;,需要 4 LCELL,CASE 段,SUBDESIGN decoder

8、(low, medium, high : input; highest_level3.0 : output; ) variable code2.0 : node; begin code2=high; code1=medium; code0=low; case code is when 4 = highest_level = B”1000”; when 2 = highest_level = B”0100”; when 1 = highest_level = B”0010”; when others = highest_level = B”0001”; end case; end;,這個(gè)段落怎么

9、用,For 循環(huán),CONSTANT num_of_bit = 8; SUBDESIGN numbit ( anum_of_bit.0 : input; bnum_of_bit.0 : output; ) begin b8 = a0; b7 = a1; b6 = a2; b5 = a3; b4 = a4; b3 = a5; b2 = a6; c1 = a7; b0 = a8; end;,寄存器邏輯,SUBDESIGN flip_flop ( d, clk : input; q : output;) begin q = dff(d,clk, ,); end;,更多的細(xì)節(jié),寄存器的更多內(nèi)容,怎樣和寄

10、存器一起使用總線 怎樣使用其他觸發(fā)器 DFFE (D-FF帶使能端) TFF/TFFE JKFF/JKFFE SRFF/SRFFE,寄存器總線,SUBDESIGN bus_reg ( clk, d7.0 : input; q7.0 : output; ) variable ff7.0 : dff; begin ff.clk = clk; ff.d = d; q = ff.q; end;,D觸發(fā)器帶使能Enable/重設(shè)Preset/清除Clear,SUBDESIGN flip_flop_enable ( clock, data, enable, preset, clear : input; q

11、out : output; ) variable temp : dffe; begin temp.d = data; temp.clk = clock; temp.clrn = clear; temp.prn = preset; temp.ena = enable; qout = temp.q; end;,D,CLK,CLRN,PRN,ENA,Q,其他類(lèi)型的觸發(fā)器,如何用幫助菜單,Q : 我不知道Altera DFF/JKFFE, 怎么辦? A : Altera幫助菜單是查找信息的好地方。 Q : 我怎樣用幫助菜單? A :這個(gè)很容易 很有趣。,DFFE,怎樣用幫助菜單,三態(tài)緩沖器,SUBDE

12、SIGN tri_state (a, enable : input; b : output;) begin b = tri(a, enable); end;,SUBDESIGN tri_state ( a, enable : input; b : output;) variable temp : tri; begin temp.in = a; temp.oe = enable; b = temp.out; end;,更多的細(xì)節(jié),OPNDRN - Open Drain Buffer,SUBDESIGN opn_drn (enable : input; b : output;) begin b =

13、 opndrn(enable); end;,SUBDESIGN tri_state ( enable : input; b : output;) variable temp : opndrn; begin temp.in= enable; b = temp.out; end;,更多的細(xì)節(jié),用AHDL 有示范性但是用AHDL 更有力,訓(xùn)練,AHDL,input,bidir,clk, enable : input; io : bidir;,設(shè)計(jì)8 位計(jì)數(shù)器很容易,SUBDESIGN 8bits (clk : input; q7.0 : output; ) variable temp7.0 : df

14、f; begin temp.clk = clk; temp.d = temp.q +1 ; q = temp.q; end;,狀態(tài)機(jī),SUBDESIGN simple ( clk, reset, jump : input; q : output; ) variable ss : MACHINE WITH STATES (S0,S1); begin ss.clk = clk; ss.reset = reset; case ss is when s0 = q = gnd; if (jump) then ss = s1; end if; when s1 = q = vcc; if (jump) th

15、en ss = s0; end if; end case; end;,狀態(tài)機(jī)圖表,注意：所有的狀態(tài)機(jī)的變量都必須 和時(shí)鐘關(guān)聯(lián)。,jump=1,jump=1,q = 0,q = 1,jump=0,jump=0,關(guān)于狀態(tài)機(jī)更多內(nèi)容,SUBDESIGN stepper ( reset, ccw, cw, clk : input; phase3.0 : output;) variable ss : MACHINE OF BITS (temp3.0) WITH STATES ( s0 = B”0001”, s1 = B”0010”, s2 = B”0100”, s3 = B”1000”); begin

16、ss.clk = clk; if (reset) then ss = s2; end if; phase = temp;,TABLE ss, ccw, cw = ss; s0, 1, x = s3; s0, x, 1 = s1; s1, 1, x = s0; s1, x, 1 = s2; s2, 1, x = s1; s2, x, 1 = s3; s3, 1, x = s2; s3, x, 1 = s0; END TABLE; end;,注意：不需要聲明什么是TEMP， 它作為DFF被自動(dòng)聲明。,用戶可以控制這些狀態(tài)位。,訓(xùn)練,SUBDESIGN stepper ( reset, ccw, c

17、w, clk : input; phase3.0 : output;) variable ss : MACHINE OF BITS (temp3.0) WITH STATES ( s0 = B”0001”, s1 = B”0010”, s2 = B”0100”, s3 = B”1000”); begin ss.clk = clk; if (reset) then ss = s2; end if; phase = temp;,TABLE ss, ccw, cw = ss; s0, 1, x = s3; s0, x, 1 = s1; s1, 1, x = s0; s1, x, 1 = s2; s2

18、, 1, x = s1; s2, x, 1 = s3; s3, 1, x = s2; s3, x, 1 = s0; END TABLE; end;,你可以到CASE段編輯真值表,狀態(tài)機(jī)沒(méi)有恢復(fù)態(tài),SUBDESIGN recover ( clk, go : input; ok : output;) variable sequence : MACHINE OF BITS (q2.0) with STATES ( idle, one, two, three, four, illegal1, illegal2, illegal3); begin sequence.clk = clk; case sequence is when idle = if (go) then sequence = one; end if; when one = sequence = two; when two = sequence = three; when three = sequence = four; end case; ok = (sequence = four); end;