數(shù)字邏輯設(shè)計(jì) - 觸發(fā)器 Flip-Flops 和時(shí)序電路

觸發(fā)器

Flip-Flops和時(shí)序電路數(shù)字系統(tǒng)設(shè)計(jì)NAND

Latch

(a)

NAND

latch;

(b)

function

table.22015

ZDMC復(fù)習(xí)數(shù)字系統(tǒng)設(shè)計(jì)NOR

Gate

Latch

(a)

NOR

gate

latch(b)

function

table(c)

simplified

blocksymbol32015

ZDMC復(fù)習(xí)42015

ZDMCMaster-Slave

Structure

Break

flow

by

alternating

clocks

(like

an

air-lock)

Use

positive

clock

to

latch

inputs

into

one

R-S

latch

Use

negative

clock

to

change

outputs

with

another

R-S

latchView

pair

as

one

basic

unit

master-slave

flip-flop

twice

as

much

logic

output

changes

a

few

gate

delays

after

the

falling

edge

of

clock

but

does

not

affect

any

cascaded

flip-flopsmaster

stageslave

stageP'P

CLK數(shù)字系統(tǒng)設(shè)計(jì)RSQ'

QRSQ'

QRS復(fù)習(xí)數(shù)字系統(tǒng)設(shè)計(jì)52015

ZDMC

脈沖觸發(fā)的觸發(fā)器一、電路結(jié)構(gòu)與工作原理提高可靠性，要求每個(gè)CLK

周期輸出狀態(tài)只能改變1次數(shù)字系統(tǒng)設(shè)計(jì)62015

ZDMC所以每個(gè)clk周期，輸出狀態(tài)只可能改變一次

1.

主從SR觸發(fā)器

(1)clk

1時(shí)，“主”按S,R翻轉(zhuǎn)，“從”保持

(2)clk下降沿到達(dá)時(shí)，“主”保持，“從”根據(jù)“主”的狀態(tài)翻轉(zhuǎn)XX00X

X0

00

11100110

00

11

01

11

01

111001*1*CLK

S

R

Q

Q*Qn0172015

ZDMC

2.

主從JK觸發(fā)器為解除約束即使出現(xiàn)S

R

1的情況下，Q*也是確定的

JK主從SRQ

Q’QQ’CLK數(shù)字系統(tǒng)設(shè)計(jì)

Q

0，“主”

1

Q

0，“主”保持0

Q

0若Q

0,則“主”置1數(shù)字系統(tǒng)設(shè)計(jì)

clk

后，“從”

1

Q*

“主”保持1

*1,主從SR

JK

Q

Q’(1)若J

1,K

0則clk

1時(shí)，QQ’CLK“主”保持

clk

后，“從”保持

Q*

1

*(3)若J

K

0則clk

1時(shí)，

clk

后，“從”

(Q*)

8(4)若J

K

1則clk

1時(shí)，若Q*

1,則“主”置0

*

2015

ZDMC

clk

后，“從”

0

Q*

1，“主”

0

*(2)若J

0,K

1則clk

1時(shí)，數(shù)字系統(tǒng)設(shè)計(jì)92015

ZDMCXX00110011CLK

J

K

Q

Q*Q*01110010XX00110011X

X0

00

10

00

11

01

11

01

1(5)

列出真值表

CLK

S

R

Q

Q*主從SRQ*0111001*1*

J

KX

X0

00

10

00

11

01

11

01

1

Q

Q’QQ’CLK11

D數(shù)字系統(tǒng)設(shè)計(jì)Clk=1RS0D’D’D

0QQ’negative

edge-triggered

D

flip-flop

(D-FF)

4-5

gate

delaysmust

respect

setup

and

hold

time

constraints

to

successfully

capture

inputcharacteristic

equation

Q(t+1)

=

Dholds

D'

whenclock

goes

lowholds

D

whenclock

goes

low

2015

ZDMCEdge-Triggered

Flip-Flops

More

efficient

solution:

only

6

gates

sensitive

to

inputs

only

near

edge

of

clock

signal

(not

while

high)復(fù)習(xí)D數(shù)字系統(tǒng)設(shè)計(jì)122015

ZDMCQClk=0

DR

S

D

D’when

clock

goes

high-to-low

data

is

latchedEdge-Triggered

Flip-Flops

(cont’d)

Step-by-step

analysisD’

D’QR

S

D

D’when

clock

is

low

data

is

heldD’D

D’

Clk=0

new

Dnew

D

old

D復(fù)習(xí)數(shù)字系統(tǒng)設(shè)計(jì)132015

ZDMCpositive

edge-triggered

FFnegative

edge-triggered

FF

QposQpos'

QnegQneg'Edge-Triggered

Flip-Flops

(cont’d)

Positive

edge-triggered

Inputs

sampled

on

rising

edge;

outputs

change

after

rising

edgeNegative

edge-triggered

flip-flops

Inputs

sampled

on

falling

edge;

outputs

change

after

falling

edge

100

D

CLK復(fù)習(xí)數(shù)字系統(tǒng)設(shè)計(jì)142015

ZDMCNegative

Edge

Trigger

FF

in

Verilog

module

d_ff

(q,

q_bar,

data,

clk);

input

data,

clk;

output

q,

q_bar;

reg

q;

assign

q_bar

=

~q;

always

@(negedge

clk)

begin

q

<=

data;

end

endmodule復(fù)習(xí)15behavior

is

the

same

unless

input

changes

while

the

clock

is

high2015

ZDMC

CLK

positiveedge-triggered

flip-flop

D

Q

G

CLK

transparent

(level-sensitive)

latch數(shù)字系統(tǒng)設(shè)計(jì)

D

CLKQedgeQlatchComparison

of

Latches

and

Flip-Flops

D

Q復(fù)習(xí)數(shù)字系統(tǒng)設(shè)計(jì)162015

ZDMCTiming

Methodologies

Rules

for

interconnecting

components

and

clocks

Guarantee

proper

operation

of

system

when

strictly

followedApproach

depends

on

building

blocks

used

for

memory

elements

Focus

on

systems

with

edge-triggered

flip-flops

–

Found

in

programmable

logic

devices

Many

custom

integrated

circuits

focus

on

level-sensitive

latchesBasic

rules

for

correct

timing:

(1)

Correct

inputs,

with

respect

to

time,

are

provided

to

the

flip-flops

(2)

No

flip-flop

changes

state

more

than

once

per

clocking

event復(fù)習(xí)17order

to

input

clockthere

is

a

timing

"window"around

the

clocking

eventduring

which

the

input

mustremain

stable

and

unchangedin數(shù)字系統(tǒng)設(shè)計(jì)

be

recognizedTsu

Thclock

stable

changing

data

clock

2015

ZDMCdataD

QD

QTiming

Methodologies

(cont’d)

Definition

of

terms

clock:

periodic

event,

causes

state

of

memory

element

to

change;

can

be

rising

or

falling

edge,

or

high

or

low

level

setup

time:

minimum

time

before

the

clocking

event

by

which

the

input

must

be

stable

(Tsu)

hold

time:

minimum

time

after

the

clocking

event

until

which

the

input

must

remain

stable

(Th)復(fù)習(xí)數(shù)字系統(tǒng)設(shè)計(jì)182015

ZDMC

IN

Q0

Q1CLK100Cascading

Edge-triggered

Flip-Flops

Shift

register

New

value

goes

into

first

stage

While

previous

value

of

first

stage

goes

into

second

stage

Consider

setup/hold/propagation

delays

(prop

must

be

>CLKINQ1hold)

Q0

D

QD

QOUT復(fù)習(xí)數(shù)字系統(tǒng)設(shè)計(jì)192015

ZDMC觸發(fā)器Flip-Flop分類

邏輯功能分類

RS鎖存器JK觸發(fā)器T觸發(fā)器D觸發(fā)器

邏輯功能指按觸發(fā)器的次態(tài)和現(xiàn)態(tài)及輸入信號之間的邏輯關(guān)系.

特性表

特性方程

狀態(tài)轉(zhuǎn)換圖復(fù)習(xí)數(shù)字系統(tǒng)設(shè)計(jì)202015

ZDMCRS

鎖存器

特性方程Qn+1=S+R’QnRS

Latch的狀態(tài)轉(zhuǎn)換圖

01S=1,R=0S=0,R=1S=X,R=0S=0,R=X特性表/真值表

S

R

Qn

Qn+1000

01111001

10011010

10101010

01100保持

復(fù)位置位不定復(fù)習(xí)數(shù)字系統(tǒng)設(shè)計(jì)212015

ZDMCJK

觸發(fā)器

特性方程:Qn+1=JQn’+K’QnJK

FF的狀態(tài)轉(zhuǎn)換圖

01J=1,K=XJ=X,K=1J=X,K=0J=0,K=X特性表/真值表

J

K

Qn

Qn+1000

01111001

10011010

10101010

01110保持

復(fù)位置位翻轉(zhuǎn)復(fù)習(xí)數(shù)字系統(tǒng)設(shè)計(jì)222015

ZDMCT

觸發(fā)器

特性方程:Qn+1=TQn’+T’QnT

FF的狀態(tài)轉(zhuǎn)換圖特性表/真值表

01T=1T=1T=0T=0TQnQn+1001

1010

1011

0保持翻轉(zhuǎn)T’觸發(fā)器：T=1,

Qn+1=Qn’

JK觸發(fā)器的兩個(gè)輸入端連在一起作為T端，可以構(gòu)成T

Flip-flop復(fù)習(xí)數(shù)字系統(tǒng)設(shè)計(jì)232015

ZDMCD

觸發(fā)器

特性方程:Qn+1=DD

FF的狀態(tài)轉(zhuǎn)換圖特性表/真值表01D=1D=1D=1D=0DQnQn+1001

1010

1001

1resetset復(fù)習(xí)數(shù)字系統(tǒng)設(shè)計(jì)242015

ZDMC本講內(nèi)容

同步時(shí)序電路分析方法數(shù)字系統(tǒng)設(shè)計(jì)25時(shí)序邏輯電路

時(shí)序電路通常包含組合電路和存儲電路兩部分.存儲電路的輸出狀態(tài)反饋到組合電路的輸入端，與輸入信號一起，共同決定組合邏輯電路的輸出.任一時(shí)刻的輸出信號不僅取決于當(dāng)時(shí)的輸入信號，還取決于電路原來的狀態(tài)（與以前的輸入有關(guān)）.組合邏輯電路

存儲電路

輸出方程Yi驅(qū)動(dòng)方程Zi輸入Xi

狀態(tài)方程

Qi時(shí)序電路的結(jié)構(gòu)框圖

2015

ZDMC數(shù)字系統(tǒng)設(shè)計(jì)262015

ZDMC時(shí)序電路分類

同步時(shí)序電路

所有觸發(fā)器狀態(tài)的變化都是在同一個(gè)時(shí)鐘信號下同時(shí)發(fā)生.異步時(shí)序電路

觸發(fā)器狀態(tài)的變化不是同時(shí)發(fā)生的.數(shù)字系統(tǒng)設(shè)計(jì)272015

ZDMCFSM:有限狀態(tài)機(jī)

采用輸入信號和電路狀態(tài)的邏輯函數(shù)去描述時(shí)序電路邏輯功能的方法Mealy型

輸出信號取決于存儲電路狀態(tài)和輸入變量Moore型

輸出只是存儲電路現(xiàn)態(tài)的函數(shù)inputsnext

statecurrent

state

輸出與時(shí)鐘同步

combinationallogicMealy

outputs

combinational

Moore

outputs

logic數(shù)字系統(tǒng)設(shè)計(jì)282015

ZDMC同步時(shí)序電路分析方法

目的是找出電路狀態(tài)和輸出信號的變換規(guī)律，指出其邏輯功能時(shí)序電路求激勵(lì)方程和輸出方程由特征方程求狀態(tài)方程求狀態(tài)表畫狀態(tài)圖畫波形圖功能描述數(shù)字系統(tǒng)設(shè)計(jì)29同步時(shí)序電路分析例D

clkD

clkQQ’QQ’xA

A’

B

B’y狀態(tài)方程:An+1=Ax+Bx

Bn+1=A’x狀態(tài)方程是確定觸發(fā)器狀態(tài)轉(zhuǎn)移條件的表達(dá)式

2015

ZDMC數(shù)字系統(tǒng)設(shè)計(jì)302015

ZDMC

輸出方程

y=(A+B)x’DQclk

Q’DQclk

Q’xAA’B

B’y數(shù)字系統(tǒng)設(shè)計(jì)312015

ZDMC狀態(tài)表描述/狀態(tài)圖現(xiàn)態(tài)輸入次態(tài)

輸出A

B

x

An+1

Bn+1

Y00000000

0101

1010

1000

1010

1001

01101100111101010010現(xiàn)態(tài)次態(tài)輸出x=0

x=1x=0

x=1ABABABY00011011000000000111101001110000000111ABx/y0/00/1

1/0101/00/11/00/11/0狀態(tài)圖數(shù)字系統(tǒng)設(shè)計(jì)322015

ZDMC由JK觸發(fā)器構(gòu)成的時(shí)序電路分析

對D觸發(fā)器,狀態(tài)方程與輸入方程一致.JK/T觸發(fā)器,參考對應(yīng)的特性表或特性方程來得到次態(tài)值.

把觸發(fā)器輸入方程表示成現(xiàn)態(tài)和輸入變量的函數(shù).

列出每個(gè)輸入方程的二進(jìn)制數(shù)值.

利用對應(yīng)觸發(fā)器的特性表確定狀態(tài)表中的次態(tài)值.數(shù)字系統(tǒng)設(shè)計(jì)332015

ZDMCJK

FF構(gòu)成的時(shí)序電路分析

JKJKCLKxABJK

FF輸入方程JA=B

KA=Bx’JB=x’

KB=A’x+Ax’數(shù)字系統(tǒng)設(shè)計(jì)342015

ZDMCJK

FF構(gòu)成的時(shí)序電路分析(續(xù))

把觸發(fā)器的輸入方程表示成現(xiàn)態(tài)和輸入變量的函數(shù).將輸入方程代入到觸發(fā)器的特性方程中,得到狀態(tài)方程.使用對應(yīng)的狀態(tài)方程確定狀態(tài)表中的次態(tài).現(xiàn)態(tài)輸入次態(tài)觸發(fā)器輸入A

B

x

A

B0

0

0

0

10

0

1

0

00

1

0

1

1

0

1

1

1

0JA001

1

KA001

0

JB101

0KB

0

1

0

1111100110101110110010010001010101010JK

FF特性方程:

Qn+1=JQn’+K’QnJK

FF輸入方程:JA=B

KA=Bx’JB=x’

KB=A’x+Ax’狀態(tài)方程:An+1=A’B+AB’+AXBn+1=B’x’+ABx+A’Bx’352015

ZDMCJK

FF構(gòu)成的時(shí)序電路分析(續(xù))1101000010

11

001

1狀態(tài)圖現(xiàn)態(tài)

輸入

次態(tài)A

B

x

A