FPGA二值圖像邊界提取算法實(shí)現(xiàn)

FPGA二值圖像邊界提取算法實(shí)現(xiàn)1背景知識圖1二值圖像邊界提取演示如圖1所示，圖1a為一幅簡單的二值圖像，經(jīng)過邊界提取后形成如圖1b所示的圖像，顯示出了白色區(qū)域的輪廓。2邊界提取算法使用黑色提取，背景為白色，‘1’表示白色，‘0’表示黑色。

圖2二值圖像邊界提取演示我們使用3x3模板進(jìn)行邊界提取，所以當(dāng)3x3九個(gè)點(diǎn)都是‘1’的時(shí)候，輸出為‘1’，當(dāng)九個(gè)點(diǎn)都是‘0’的時(shí)候，輸出為‘1’，其他情況輸出均為‘0’。3FPGA二值圖像邊界提取算法實(shí)現(xiàn)圖2二值圖像膨脹FPGA模塊架構(gòu)圖2中我們使用串口傳圖傳入的是二值圖像。

FPGA源碼：

/*

Modulename:

boundary_extraction.v

Description:

binaryimageboundaryextraction

*/

`timescale1ns/1ps

moduleboundary_extraction(

input

clk,

//pixelclk

input

rst_n,

input

hs_in,

input

vs_in,

input[15:0]

data_in,

input

data_in_en,

output

hs_out,

output

vs_out,

output

reg[15:0]

data_out,

output

data_out_en

);

wire[15:0]line0;

wire[15:0]line1;

wire[15:0]line2;

reg[15:0]line0_data0;

reg[15:0]line0_data1;

reg[15:0]line0_data2;

reg[15:0]line1_data0;

reg[15:0]line1_data1;

reg[15:0]line1_data2;

reg[15:0]line2_data0;

reg[15:0]line2_data1;

reg[15:0]line2_data2;

reg

data_out_en0;

reg

data_out_en1;

reg

data_out_en2;

reg

hs_r0;

reg

hs_r1;

reg

hs_r2;

reg

vs_r0;

reg

vs_r1;

reg

vs_r2;

wire[18:0]

result_data;

line3x3line3x3_inst(

.clken(data_in_en),

.clock(clk),

.shiftin(data_in),

.shiftout(),

.taps0x(line0),

.taps1x(line1),

.taps2x(line2)

);

//------------------------------------------------------------------------------

//Formanimagematrixofthreemultipliedbythree

//------------------------------------------------------------------------------

always@(posedgeclkornegedgerst_n)begin

if(!rst_n)begin

line0_data0<=16'b0;

line0_data1<=16'b0;

line0_data2<=16'b0;

line1_data0<=16'b0;

line1_data1<=16'b0;

line1_data2<=16'b0;

line2_data0<=16'b0;

line2_data1<=16'b0;

line2_data2<=16'b0;

data_out_en0<=1'b0;

data_out_en1<=1'b0;

data_out_en2<=1'b0;

hs_r0<=1'b0;

hs_r1<=1'b0;

hs_r2<=1'b0;

vs_r0<=1'b0;

vs_r1<=1'b0;

vs_r2<=1'b0;

end

elseif(data_in_en)begin

line0_data0<=line0;

line0_data1<=line0_data0;

line0_data2<=line0_data1;

line1_data0<=line1;

line1_data1<=line1_data0;

line1_data2<=line1_data1;

line2_data0<=line2;

line2_data1<=line2_data0;

line2_data2<=line2_data1;

data_out_en0<=data_in_en;

data_out_en1<=data_out_en0;

data_out_en2<=data_out_en1;

hs_r0<=hs_in;

hs_r1<=hs_r0;

hs_r2<=hs_r1;

vs_r0<=vs_in;

vs_r1<=vs_r0;

vs_r2<=vs_r1;

end

end

//-------------------------------------------------------------------

//line0_data0

line0_data1

line0_data2

//line1_data0

line1_data1

line1_data2

//line2_data0

line2_data1

line2_data2

//--------------------------------------------------------------------

always@(posedgeclkornegedgerst_n)begin

if(!rst_n)

data_out<=16'h0000;

elseif(data_out_en1)

if((line0_data0==16'h0000)&&(line0_data1==16'h0000)&&(line0_data2==16'h0000)&&(line1_data0==16'h0000)&&(line1_data1==16'h0000)&&(line1_data2==16'h0000)&&(line2_data0==16'h0000)&&(line2_data1==16'h0000)&&(line2_data2==16'h0000))

data_out<=16'hffff;

elseif((line0_data0==16'hffff)&&(line0_data1==16'hffff)&&(line0_data2==16'hffff)&&(line1_data0==16'hffff)&&(line1_data1==16'hffff)&&(line1_data2==16'hffff)&&(line2_data0==16'hffff)&&(line2_data1==16'hffff)&&(line2_data2==16'hffff))

data_out<=16'hffff;

else