超大規(guī)模集成電路第九次作業(yè)2016秋-段成華

Assignment91.Designan8-bitupanddownsynchronouscounterinVHDLwiththefollowingfeatures:Thesameportsareusedforsignalstobeinputtedandoutputted.Theportsarebi-directionallybuffered(three-state).Thecounteriswithanasynchronousresetthatassignsaspecificinitialvalueforcounting.Thecounteriswithasynchronousdataloadcontrolinputforanewvalueofcountingandanenablecontrolinputforallowingtheupanddowncounting.Theloadcontrolinputhasapriorityovertheenablecontrolinput.Thisimpliesthatwhentheloadoperationisinprocessthecounteroperationisprohibited.Somedatatypes,suchasSTD_LOGIC,UNSIGNED,SIGNEDandINTEGER,maybeused.Synthesizethedesign.Createasetofreasonableinputwaveformsforyourdesignandcompletebothbehavioralandpost-place&routesimulationswithinternalsignalsand/orvariablesincludedinwaveformorlistwindows.Solution:代碼如下：libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;----Uncommentthefollowinglibrarydeclarationifinstantiating----anyXilinxprimitivesinthiscode.--libraryUNISIM;--useUNISIM.VComponents.all;entitycount_8_bidirisPort( clk:inSTD_LOGIC;rst:inSTD_LOGIC;load:inSTD_LOGIC;enable:inSTD_LOGIC;cnt:inoutSTD_LOGIC_VECTOR(7downto0));endcount_8_bidir;architectureBehavioralofcount_8_bidirissignalcnt_in:STD_LOGIC_VECTOR(7downto0);signalcnt_out:STD_LOGIC_VECTOR(7downto0);beginpro0:process(oe,cnt_out,cnt) beginif(load='1')then cnt<=(others=>'Z');cnt_in<=cnt; else cnt<=cnt_out; endif; endprocess; pro1:process(clk,rst) begin if(rst='1')then cnt_out<=(others=>'0'); elsifrising_edge(clk)then if(load='1')thencnt_out<=cnt_in; elsif(enable='1')then cnt_out<=cnt_out+1; elsecnt_out<=cnt_out-1; endif; endif; endprocess;endBehavioral;解釋代碼：這里有兩個進(jìn)程，進(jìn)程0時是用來控制三態(tài)門控制的雙向端口。當(dāng)cnt作為輸入時（load='1'），把cnt賦給cnt_in（初值裝載），然后置cnt為高阻狀態(tài)；否則，即cnt作為輸出時（load='0'），把cnt_out（計數(shù)器計數(shù)輸出值）賦給cnt。進(jìn)程1的作用是：當(dāng)復(fù)位信號rst='1'，計數(shù)器輸出cnt_out為全0，否則在時鐘的上升沿檢測cnt端口是作為輸入還是作為輸出，當(dāng)作為輸入時（load='1'），把cnt_in中的數(shù)取進(jìn)來，然后當(dāng)up_down='0'時，進(jìn)行加法運(yùn)算，否則做減法運(yùn)算，同時可以和進(jìn)程0配合當(dāng)load='0'，將數(shù)值從cnt_out輸出到cnt。TestBench代碼：LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.all;USEieee.numeric_std.ALL;ENTITYcount_8_bidir_tbISENDcount_8_bidir_tb;ARCHITECTUREbehaviorOFcount_8_bidir_tbIS--ComponentDeclarationfortheUnitUnderTest(UUT)COMPONENTcount_8_bidirPORT(oe:INstd_logic;clk:INstd_logic;rst:INstd_logic;load:INstd_logic;enable:INstd_logic;圖1圖2ForCPLDimplementation(fit)oftheFIFOs,howmanyMCs(macrocells)andPTs(productterms)areneeded?Whichparameteriscriticaltothemaximuminternalclockworkingfrequency?Trytofindoutthiscriticalparameteranditscorrespondingcircuitpath.設(shè)置芯片為CoolRunnerXPLA3CPLDS系XCR3512XL-7-PQ208，速度為-7，綜合后報告分析如下

圖3為CPLD綜合報告：從報告中可以知道一共使用了87個MCs，占總體的17%，使用了208個PTs，占總體的14%，選這個型號似乎有點(diǎn)大材小用啊，不過資源很足夠，滿足設(shè)計的需求。圖4為CPLD時間報告：由圖4可知，時鐘的最小周期為8.6ns，受clocktosetup影響最大，故關(guān)鍵路徑為tcyc。延時為8.6ns，時鐘的工作頻率為116.279MHz。圖3圖4ForFPGAimplementation(placeandroute)oftheFIFOs,howmanyLBs(logicblocks)?Whichparameteriscriticaltothemaximuminternalclockworkingfrequency?Trytofindoutthiscriticalparameteranditscorrespondingcircuitpath.設(shè)置芯片為更換芯片型號為Spartan3-xc3s200-5pq208,速度為-5，其綜合報告如下圖5為FPGA綜合報告：圖5圖6為Spartan3datasheet圖6圖7由上圖知，對于選擇的器件，其logiccell為4320,CLB有24X20=480個，每個CLB包含4個slice,而對于我們的程序，一共使用了66個slice，占總數(shù)的百分之三（總slice共計1920個），故使用的CLB數(shù)為66/4=16.5，即使用了17個。由圖7可知，時鐘的最小周期為5.078ns，受clocktosetup影響最大，時鐘的工作頻率為196.927MHz。Trytosynthesizeagainthedesignwithtimingconstraintsandcomparewithitsformercounterparts.Youwillcreatethetimingconstraintfilebyyourselfandaddittoyourproject.PleaserefertothefollowinggraphicinterfaceofISE:圖8為timingconstrain設(shè)置圖；圖9為沒有設(shè)置時序約束時的報告；圖10為設(shè)置CLK周期約束為5ns時的報告；圖11為設(shè)置CLK周期約束為4.5ns時的報告；圖12設(shè)置clk周期約束為4ns時的報告圖13設(shè)置clk周期約束為3.5ns時的報告圖8圖9圖10圖11圖12圖13FortheVHDLmodelgivenbelow(CodeListTwo),theremaybesomedesignerrorsinit.Somewarning(s)and/orerror(s)informationmaybeissuedwhensynthesizingit.Trytofindoutsuchdesignerrorsandcorrectthem.仿真后無錯誤，有兩個警告如下圖：圖14(1)程序中，輸入端口rd沒有使用到，其作用被oe所取代，因此可以將rd信號去掉，用oe來表示其功能，且不影響整個系統(tǒng)的設(shè)計。(2)程序中輸入信號端口en也未被使用，因?yàn)橹苯釉趂ifo(wrptr)中取得了寫地址的值，因此信號en也應(yīng)去掉。(3)語句dmuxout<=fifo(wrptr);應(yīng)改為dmuxout<=fifo(rdptr);因?yàn)檫@時是讀寄存器里的值，應(yīng)該由讀地址指針rdptr來指定應(yīng)該讀取哪個寄存器的值。改進(jìn)后加入激勵得到圖15的輸出波形。圖158X9FIFOBUFFERDESIGNEXAMPLES1#VHDLCODELIST:libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityfifo89isPort(clk:instd_logic;rst:instd_logic;rd:instd_logic;wr:instd_logic;rdinc:instd_logic;wrinc:instd_logic;rdptrclr:instd_logic;wrptrclr:instd_logic;data_in:instd_logic_vector(8downto0);data_out:outstd_logic_vector(8downto0));endfifo89;--clk:usedtosynchronizethebuffers;--rst:resetthebuffers--rd:whenvalid,theoutputbuffersareenabled;--wr:whenvalid,writeregisterwith9-bitwidthispermitted;--rdinc:readcounterenabled;--wrinc:writecounterenabled;--rdptrclr:resetreadcounter,pointingtothefirstregisterfor--readpurpose;--wrptrclr:resetwritecounter,pointingtothefirstregisterfor--writepurpose;--data_in:datainputswith9-bitwidthtotheFIFOs;--data_out:dataoutputswith9-bitwidthfromtheFIFOs.architectureBehavioraloffifo89is typefifo_arrayisarray(7downto0)ofstd_logic_vector(8downto0); signalfifo:fifo_array; signalwrptr,rdptr:std_logic_vector(2downto0); signalen:std_logic_vector(7downto0); signaldmuxout:std_logic_vector(8downto0);begin--fiforegister_array:reg_array:process(rst,clk) begin ifrst='1'then foriin7downto0loop fifo(i)<=(others=>'0');--aggregate endloop; elsif(clk'eventandclk='1')then ifwr='1'then foriin7downto0loop ifen(i)='1'then fifo(i)<=data_in; else fifo(i)<=fifo(i); endif; endloop; endif; endif; endprocess;--readpointerread_count:process(rst,clk) begin ifrst='1'then rdptr<=(others=>'0'); elsif(clk'eventandclk='1')then ifrdptrclr='1'then rdptr<=(others=>'0'); elsifrdinc='1'then rdptr<=rdptr+1; endif; endif; endprocess;--writepointerwrite_count:process(rst,clk) begin ifrst='1'then wrptr<=(others=>'0'); elsif(clk'eventandclk='1')then ifwrptrclr='1'then wrptr<=(others=>'0'); elsifwrinc='1'then wrptr<=wrptr+1; endif; endif; endprocess;--8:1outputdatamuxwithrdptrselect dmuxout<=fifo(0)when"000", fifo(1)when"001", fifo(2)when"010", fifo(3)when"011", fifo(4)when"100", fifo(5)when"101", fifo(6)when"110", fifo(7)whenothers;--FIFOregisterselectordecoderwithwrptrselect en<="00000001"when"000", "00000010"when"001", "00000100"when"010", "00001000"when"011", "00010000"when"100", "00100000"when"101", "01000000"when"110", "10000000"whenothers;--three-statecontrolofoutputsthree_state:process(rd,dmuxout) begin ifrd='1'then data_out<=dmuxout; else data_out<=(others=>'Z'); endif; endprocess;endBehavioral;2#VHDLCODELIST:libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityfifoxyisgeneric(wide:integer:=8);--widthis8+1Port(clk:instd_logic;rst:instd_logic; oe:instd_logic;rd:instd_logic;wr:instd_logic;rdinc:instd_logic;wrinc:instd_logic;rdptrclr:instd_logic;wrptrclr:instd_logic;data_in:instd_logic_vector(widedownto0);data_out:outstd_logic_vector(widedownto0));endfifoxy;architectureArchfifoxyoffifoxyis constantdeep:integer:=7;--depthis7+1 typefifo_arrayisarray(deepdownto0)ofstd_logic_vector(widedownto0); signalfifo:fifo_array; signalwrptr,rdptr:integerrange0todeep; signalen:std_logic_vector(deepdownto0); signaldmuxout:std_logic_vector(widedownto0