PARWAN-CPU-狀態(tài)機設(shè)計說明書

/基于FPGA的數(shù)字系統(tǒng)設(shè)計大作業(yè)學(xué)號：13091378 姓名：邢武天 班級：130914題目一：設(shè)計Parwan的controlsection內(nèi)部狀態(tài)機s1\s2\..\s9\,并給出功能仿真？題目二：利用分層結(jié)構(gòu)設(shè)計ParwanCPU,并給出功能仿真?〔利用在實驗課中所給出的TESTBENCH實驗原理圖ControlSectionStructure：s1…s9〔如下圖所示InputsandoutputsofPARWANcontrolsections:–Appliedto,categories,signalname,functions實驗過程1.1創(chuàng)建工程〔1 打開ISE13.x軟件.選擇File->NewProject在彈出的對話框中輸入工程名和路徑?！? 單擊下一步選擇所使用的芯片。Spartan3E開發(fā)板的芯片型號為Spartan3EXC3S500E芯片.FG320封裝?！? 單擊Next.進入工程信息頁面.確認無誤后.點擊Finish完成工程的創(chuàng)建。1.2測試文件<1>選擇菜單欄中的Project->NewSource。<2>在SelectSourceType窗口中.選擇左側(cè)的VHDLTestBench,在右側(cè)FileName欄中輸入文件名par_control_unit_tb<3>單擊Next按鈕.選擇關(guān)聯(lián)文件。1.3實驗截圖實驗代碼在實現(xiàn)過程中.除了定義CPU的信號接口外.還設(shè)置了一個輸出類型的接口.名字叫present_state_value,主要是用來在調(diào)試或仿真的過程中輸出CPU所處的狀態(tài).便于調(diào)試分析。整個狀態(tài)機的實現(xiàn)過程主要使用了case…IS…when邏輯結(jié)構(gòu)。用了present_state和next_state兩個狀態(tài)變量。詳細的實現(xiàn)代碼如下所示：LIBRARYIEEE;USEIEEE.std_logic_1164.ALL;USEwork.synthesis_utilities.ALL;--ENTITYpar_control_unitISPORT<clk:INstd_logic;--registercontrolsignals:load_ac,zero_ac,load_ir,increment_pc,load_page_pc,load_offset_pc,reset_pc,load_page_mar,load_offset_mar,load_sr,cm_carry_sr,--busconnectioncontrolsignals:pc_on_mar_page_bus,ir_on_mar_page_bus,pc_on_mar_offset_bus,dbus_on_mar_offset_bus,pc_offset_on_dbus,obus_on_dbus,databus_on_dbus,mar_on_adbus,dbus_on_databus,--logicunitfunctioncontroloutputs:arith_shift_left,arith_shift_right:OUTstd_logic;alu_and,alu_not,alu_a,alu_add,alu_b,alu_sub:outstd_logic;--inputsfromthedatasection:ir_lines:INstd_logic_vector<7DOWNTO0>;status:INstd_logic_vector<3DOWNTO0>;--memorycontrolandotherexternalsignals:read_mem,write_mem:OUTstd_logic;interrupt:INstd_logic; --test present_state_value:outstd_logic_vector<3DOWNTO0>>;ENDpar_control_unit;--ARCHITECTUREdataflow_synthesizableOFpar_control_unitISTYPEcpu_statesIS<s1,s2,s3,s4,s5,s6,s7,s8,s9>;SIGNALpresent_state,next_state:cpu_states; SIGNALnext_state_value:std_logic_vector<3DOWNTO0>;BEGINclocking:PROCESS<clk,interrupt>BEGINIF<interrupt='1'>THENpresent_state<=s1; present_state_value<="0001";ELSIFclk'EVENTANDclk='0'THENpresent_state<=next_state; present_state_value<=next_state_value;ENDIF;ENDPROCESSclocking;--sequencing:PROCESS<present_state,ir_lines,status,interrupt>BEGINload_ac<='0';zero_ac<='0';load_ir<='0';increment_pc<='0';load_page_pc<='0';load_offset_pc<='0';reset_pc<='0';load_page_mar<='0';load_offset_mar<='0';load_sr<='0';cm_carry_sr<='0';--busconnectioncontrolsignals:pc_on_mar_page_bus<='0';ir_on_mar_page_bus<='0';pc_on_mar_offset_bus<='0';dbus_on_mar_offset_bus<='0';pc_offset_on_dbus<='0';obus_on_dbus<='0';databus_on_dbus<='0';mar_on_adbus<='0';dbus_on_databus<='0';--logicunitfunctioncontroloutputs:arith_shift_left<='0';arith_shift_right<='0';alu_and<='0';alu_not<='0';alu_a<='0';alu_add<='0';alu_b<='0';alu_sub<='0';--memorycontrolandotherexternalsignals:read_mem<='0';write_mem<='0';CASEpresent_stateISWHENs1=>1IF<interrupt='1'>THENreset_pc<='1';next_state<=s1; next_state_value<="0001";ELSEpc_on_mar_page_bus<='1';pc_on_mar_offset_bus<='1';load_page_mar<='1';load_offset_mar<='1';next_state<=s2; next_state_value<="0010";ENDIF;WHENs2=>2--readmemoryintoirmar_on_adbus<='1';read_mem<='1';databus_on_dbus<='1';alu_a<='1'; load_ir<='1';increment_pc<='1';next_state<=s3; next_state_value<="0011";WHENs3=>3pc_on_mar_page_bus<='1';pc_on_mar_offset_bus<='1';load_page_mar<='1';load_offset_mar<='1';IF<ir_lines<7DOWNTO4>/="1110">THENnext_state<=s4; next_state_value<="0100";ELSECASEir_lines<3DOWNTO0>ISWHEN"0001"=>--clazero_ac<='1';load_ac<='1'; WHEN"0100"=>--cmccm_carry_sr<='1';WHEN"1000"=>--aslalu_b<='1';arith_shift_left<='1';load_sr<='1';load_ac<='1';WHEN"1001"=>--asralu_b<='1';arith_shift_right<='1';load_sr<='1';load_ac<='1';WHENOTHERS=>NULL;ENDCASE;next_state<=s2; next_state_value<="0010";ENDIF;WHENs4=>4--readmemoryintomaroffsetmar_on_adbus<='1';read_mem<='1';databus_on_dbus<='1';dbus_on_mar_offset_bus<='1';load_offset_mar<='1';IF<ir_lines<7DOWNTO6>/="11">THENir_on_mar_page_bus<='1';load_page_mar<='1';IF<ir_lines<4>='1'>THEN next_state<=s5; next_state_value<="0101"; ELSEnext_state<=s6; next_state_value<="0110";ENDIF;ELSE--jsrorbra,donotaltermar--pageIF<ir_lines<5>='0'>THEN--jsrnext_state<=s7; next_state_value<="0111";ELSEnext_state<=s9; next_state_value<="1001"; ENDIF;ENDIF;increment_pc<='1';WHENs5=>5--readactualoperandfrommemoryintomar--offset mar_on_adbus<='1';read_mem<='1';databus_on_dbus<='1';dbus_on_mar_offset_bus<='1';load_offset_mar<='1';next_state<=s6; next_state_value<="0110";WHENs6=>6IF<ir_lines<7DOWNTO5>="100">THEN--jmpload_page_pc<='1';load_offset_pc<='1';next_state<=s2; next_state_value<="0010";ELSIF<ir_lines<7DOWNTO5>="101">THEN--maronadbus,acondatabus,write--tomemorymar_on_adbus<='1';alu_b<='1';obus_on_dbus<='1';dbus_on_databus<='1';write_mem<='1';next_state<=s1; next_state_value<="0001";ELSIF<ir_lines<7>='0'>THEN--lda,and,add,sub--maronadbus,readmemoryfor--operand,performoperationmar_on_adbus<='1';read_mem<='1';databus_on_dbus<='1';IF<ir_lines<6>='0'>THEN lda,and IF<ir_lines<5>='0'> THEN--lda alu_a<='1'; ELSE--and alu_and<='1';ENDIF;ELSEadd,subIF<ir_lines<5>='0'>THEN--addalu_add<='1';ELSE--subalu_sub<='1';ENDIF;ENDIF;load_sr<='1';load_ac<='1';next_state<=s1; next_state_value<="0001";ENDIF;WHENs7=>7--writepcoffsettotopofsubroutinemar_on_adbus<='1';pc_offset_on_dbus<='1';dbus_on_databus<='1';write_mem<='1';load_offset_pc<='1';next_state<=s8; next_state_value<="1000";WHENs8=>8increment_pc<='1';next_state<=s1; next_state_value<="0001";WHENs9=>9IF<all_or<statusANDir_lines<3DOWNTO0>>='1'>THENload_offset_pc<='1';ENDIF;next_state<=s1; next_state_value<="0001";實驗原理實驗過程創(chuàng)建工程〔1 打開ISE13.x軟件.選擇File->NewProject在彈出的對話框中輸入工程名和路徑?！? 單擊下一步選擇所使用的芯片。Spartan3E開發(fā)板的芯片型號為Spartan3EXC3S500E芯片.FG320封裝?！? 單擊Next.進入工程信息頁面.確認無誤后.點擊Finish完成工程的創(chuàng)建。設(shè)計輸入選擇Project->Addcopyofsource.將實驗的源代碼添加到工程中。綜合實現(xiàn)編寫匯編測試代碼〔2用文本編輯器打開實驗源代碼中的simple.asm文件。〔3將測試代碼轉(zhuǎn)換為內(nèi)存文件〔4編譯并執(zhí)行程序設(shè)計仿真結(jié)果截圖編寫testbench代碼對以上的狀態(tài)機進行功能仿真。Testbench的核心代碼如下：stim_proc:processbegin --