vlsi電路及系統(tǒng)設(shè)計課程內(nèi)容與學(xué)時分配

課程內(nèi)容與學(xué)時第0（3學(xué)時第1部分MOS器件按比例縮小及其對VLSI的影響（12學(xué)時第2部分VLSI電路分析與設(shè)計（12學(xué)時第3VLSI運(yùn)算電路分析與設(shè)計（9學(xué)時第4VLSI控制電路分析與設(shè)計（3學(xué)時第5VLSI設(shè)計方法學(xué)（3學(xué)時第6SOI、BiCMOS和納米CMOS技術(shù)（6學(xué)時

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課程內(nèi)容與學(xué)時第1MOS器件按比例縮小及其對VLSI★第1講按比例縮小理★第2講高場效應(yīng)對小尺寸器件性能的★第3講器件參數(shù)漲落的影★第4講寄生效應(yīng)的

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器件參數(shù)漲落的★L(fēng)ot-to-Lot/Wafer-to-Wafer→Die-to-Die/Within-Die-to-Die-to-Within-Wafer-to-Source:NassifS.Delayvariability:sources,impactandtrends.ISSCC,2000,

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器件參數(shù)漲落的

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雜質(zhì)隨機(jī)分布（Random Distribution,★溝道區(qū)內(nèi)的雜質(zhì)原子總數(shù)只有幾十個到幾百個★雜質(zhì)數(shù)目太少，其數(shù)量的相對起伏★隨機(jī)本質(zhì)★1 2 C2 ox C2

F MSF

C

kTlnNAi i

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★3種溝道長0.7μm,0.5μm,★3種摻雜濃4.3×1016cm-3,7.1×1016cm-1.4×1017cm-★L(fēng)eff=0.5μm的陣列★L(fēng)eff=0.3μm的陣列Source:MizunoT,etal.ExperimentalStudyofThresholdVoltageFluctuationDuetoStatisticalVariationofChannelNumberinMOSFET’s.IEEETrans.onElectronDevices,1994,41(11):

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i ★測量

A i oxA220siq2F 2F2 A2.4%NA★每個MOSFET溝道區(qū)平均雜質(zhì)原★計算得

i i

Weff

i a

2.3%

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★只考慮耗盡層電荷數(shù) σQB

tox 1 Ttox

C 2ε0εox4ε0εoxqNA2ε0εox

NALeffWeffxdm44ε q3φ 4

4ε

xd

ε0

Leff

qNA Source:MizunoT,etal.ExperimentalStudyofThresholdVoltageFluctuationDuetoStatisticalVariationofChannelNumberinMOSFET’s.IEEETrans.onElectronDevices,1994,41(11):

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★考慮耗盡層電荷數(shù)起伏+44ε q

kT

4σVT

F

4ε0εoxqNA

ε0εox

Leff44ε q3φ 4 F ε0εox

LeffSource:StolkPA,etal.ModelingStatisticalDopantFluctuationsinMOSTransistors.IEEETrans.onElectronDevices,1998,

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三維原子化（3DAtomistic）★基本n3求解三維的泊松方程，表示每個雜質(zhì)原子相聯(lián)系的電勢和電

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3DAtomistic器件模擬—實(shí)驗★實(shí)驗NA=5×1018cm-★閾值電壓均值的Source:AsenovA.RandomDopantInducedThresholdVoltageLoweringandFluctuationsinSub‐0.1μmMOSFET’s:A3‐D“Atomistic”SimulationStudy.IEEETrans.onElectronDevices,1998,45(12):2505‐2513

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3DAtomistic器件模擬—實(shí)驗★2500個不同雜質(zhì)分布的MOSFET★溝道耗盡層內(nèi)平均的雜質(zhì)原子數(shù)為★對于同樣的雜質(zhì)總數(shù)，閾值電壓也有明顯的離散，說明雜質(zhì)原子微觀的隨Source:AsenovA.RandomDopantInducedThresholdVoltageLoweringandFluctuationsinSub‐0.1μmMOSFET’s:A3‐D“Atomistic”SimulationStudy.IEEETrans.onElectronDevices,1998,45(12):2505‐2513

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3DAtomistic器件模擬—實(shí)驗★實(shí)驗?zāi)康模弘s質(zhì)隨機(jī)分布對16nmMOS器件和電路的影★實(shí)驗?zāi)Ｐ停篧=L=16nm,★16nm3的小立方體中125個雜質(zhì)原子,雜質(zhì)數(shù)目起伏為0~14,均值為Source:LiY,etal.Random‐Dopant‐InducedVariabilityinNano‐CMOSDevicesandDigitalCircuits.IEEETrans.onElectronDevices,2009,56(8):1588‐1597

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3DAtomistic器件模擬—實(shí)驗★<tr>=1.02ps,σtr=0.036ps，<tf>=0.89ps,Source:LiY,etal.Random‐Dopant‐InducedVariabilityinNano‐CMOSDevicesandDigitalCircuits.IEEETrans.onElectronDevices,2009,56(8):1588‐1597

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3DAtomistic器件模擬—實(shí)驗★邏輯門的特(unit:Source:LiY,etal.Random‐Dopant‐InducedVariabilityinNano‐CMOSDevicesandDigitalCircuits.IEEETrans.onElectronDevices,2009,56(8):1588‐1597

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★閾值電壓起伏變化厚度為d的耗盡層，從Si/SiO2Source:AsenovA.RandomDopantInducedThresholdVoltageLoweringandFluctuationsinSub‐0.1μmMOSFET’s:A

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★逆向摻雜(Retrograde 3 2

1 s dxs是表面輕摻雜區(qū)的厚度，xdSource:StolkPA,etal.ModelingStatisticalDopantFluctuationsinMOSTransistors.IEEETrans.onElectronDevices,1998,

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器件參數(shù)漲落的

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柵線條邊沿粗糙度（LineEdgeRoughness★L(fēng)ER~~5nm《----》Lg=0.5μmvsSource:CroonJA,etal.LineEdgeRoughness:Characterization,ModelingandImpactonDeviceBehavior.IEDM,2002,

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Source:AsenovA,etal.IntrinsicParameterFluctuationsinDecananometerMOSFETsIntroducedbyGateLineEdgeIEEETrans.onElectronDevices,2003,50(5):

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LER的表★邊沿粗糙度 值?，通常用3?來表示LER的大1Δ1 1 δ i

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LER的表★線條寬度粗糙(LineWidthRoughness,1

2Δ

ni

LgiLggLgi是某一測量點(diǎn)的柵線條寬度，Lgρ是兩條邊粗Source:KimS‐D,etal.TCAD‐Based ysisandModelingofGateLine‐EdgeRoughnessEffectonNanoscale

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用2-D模擬柵LER的影★MSource:CroonJA,etal.LineEdgeRoughness:Characterization,ModelingandImpactonDeviceBehavior.IEDM,2002,

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用2-D模擬柵LER的影響（續(xù)★L(fēng)g=80nm,3?=5.7nm,?W=7nm,★器件參數(shù)變化的標(biāo)準(zhǔn)偏差隨著器件寬度減小而顯著增★L(fēng)ER增大對導(dǎo)通電Source:OldigesP,etal.ModelingLineEdgeRoughnessEffectsinsub100NanometerGateLengthDevices.Proc.SISPAD, 微納電子 — 用3-D模擬柵LER的影★隨著柵LER增大，閾值電壓均值下降、偏差加大，IoffSource:AsenovA,etal.IntrinsicParameterFluctuationsinDecananometerMOSFETsIntroducedbyGateLineEdgeRoughness.IEEETrans.onElectronDevices,2003,50(5):1254‐1260

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★UTBSOI器件受LER的影響遠(yuǎn)小于其他器器件結(jié)體LP體UTBSOI樣本Source:ReidD,etal.UnderstandingLER‐InducedMOSFETVTVariability‐‐‐‐Part1:Three‐DimensionalSimulationofLargeStatisticalSamples.IEEETrans.onElectronDevices,2010,57(11):2801‐2807

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Source:SunX,etal.SpacerGateLithographyforReducedVariabilityDuetoLineEdgeRoughness.IEEETran.SemiconductorManufacturing,2010,23(2):311‐315

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32nm14nmSource:SunX,etal.SpacerGateLithographyforReducedVariabilityDuetoLineEdgeRoughness.IEEETran.SemiconductorManufacturing,2010,23(2):311‐315

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器件參數(shù)漲落的

微納電子學(xué)—

其他工藝因素的★雜質(zhì)隨機(jī)分布★柵材料的功函數(shù)變化★柵氧化層厚度變化

微納電子學(xué)—

其他工藝因素的★柵材料晶粒的晶向隨機(jī)性引起功函數(shù)的變TMS TMSSource:YuC‐H,etal.StatisticalSimulationofMetal‐GateWork‐functionFluctuationinHigh‐k/Metal‐GateDevice