FPGA的電子鐘設(shè)計(jì)VHDL語言

-.z引言：近年來,隨著數(shù)字集成電路技術(shù)的開展,用以前傳統(tǒng)的方法進(jìn)展芯片或系統(tǒng)設(shè)計(jì)已不能滿足要求,迫切需要提高設(shè)計(jì)效率。能大大降低設(shè)計(jì)難度的VHDL設(shè)計(jì)方法正在被越來越廣泛的采用。VHDL即超高速集成電路硬件描述語言,誕生于1982年。1987年底,VHDL被IEEE和美國國防部確認(rèn)為標(biāo)準(zhǔn)硬件描述語言。此后VHDL在電子設(shè)計(jì)領(lǐng)域得到了廣泛的承受,并逐步取代了原有的非標(biāo)準(zhǔn)的硬件描述語言。1993年IEEE對VHDL進(jìn)展了修訂,從更高的抽象層次和系統(tǒng)描述能力上擴(kuò)展VHDL的內(nèi)容,公布了新版本的VHDL，即IEEE標(biāo)準(zhǔn)的1076--1993版本?，F(xiàn)在,VHDL作為IEEE的工業(yè)標(biāo)準(zhǔn)硬件描述語言,已成為通用硬件描述語言。關(guān)鍵字：電子鐘、FPGA、VHDL語言前言：現(xiàn)在電子鐘產(chǎn)品可謂百家爭鳴，市場上到處可見一些功能齊全的設(shè)備，可能基于單片機(jī)的比擬多，用FPGA設(shè)計(jì)電子鐘可能比擬少。因?yàn)閮蓚€(gè)都可以實(shí)現(xiàn)同樣的功能，而FPGA芯片的價(jià)格遠(yuǎn)比單片機(jī)高。出于利潤，當(dāng)然會(huì)選擇開發(fā)本錢少的產(chǎn)品。本次設(shè)計(jì)的目的是為了檢驗(yàn)所學(xué)的知識(shí)〔VHDL語言〕同時(shí)結(jié)合實(shí)踐穩(wěn)固知識(shí)，由于初涉該領(lǐng)域，相關(guān)的知識(shí)可能不夠全面，實(shí)踐的經(jīng)歷不夠，所以本設(shè)計(jì)旨在能夠?qū)崿F(xiàn)該功能并到達(dá)一定的精度，對于各模塊設(shè)計(jì)的優(yōu)化和性能等方面沒有多加考慮。為提高精度，所以本設(shè)計(jì)采用12MHZ的CLK信號(hào)，這樣產(chǎn)生的誤差也較小。一、設(shè)計(jì)目的1、掌握各類計(jì)數(shù)器及將它們相連的方法；2、掌握多個(gè)數(shù)碼管動(dòng)態(tài)顯示的原理和方法3、掌握FPGA技術(shù)層次化設(shè)計(jì)4、進(jìn)一步了解VHDL硬件描述語言的設(shè)計(jì)思想5、了解有關(guān)數(shù)字系統(tǒng)的設(shè)計(jì)二、設(shè)計(jì)原理：數(shù)字鐘電路的根本構(gòu)造由兩個(gè)60進(jìn)制計(jì)數(shù)器和一個(gè)24進(jìn)制計(jì)數(shù)器組成，分別對秒、分、小時(shí)進(jìn)展計(jì)時(shí)，當(dāng)計(jì)時(shí)到23時(shí)59分59秒時(shí)，再來一個(gè)計(jì)數(shù)脈沖，則計(jì)數(shù)器清零，重新開場計(jì)時(shí)。秒計(jì)數(shù)器的計(jì)數(shù)時(shí)鐘CLK為1Hz的標(biāo)準(zhǔn)信號(hào)，可以由晶振產(chǎn)生的24MHz信號(hào)通過分頻得到。當(dāng)數(shù)字鐘處于計(jì)時(shí)狀態(tài)時(shí)，秒計(jì)數(shù)器的進(jìn)位輸出信號(hào)作為分鐘計(jì)數(shù)器的計(jì)數(shù)信號(hào)，分鐘計(jì)數(shù)器的進(jìn)位輸出信號(hào)又作為小時(shí)計(jì)數(shù)器的計(jì)數(shù)信號(hào)時(shí)、分、秒的計(jì)時(shí)結(jié)果通過6個(gè)數(shù)碼管來動(dòng)態(tài)顯示。數(shù)字鐘除了能夠正常計(jì)時(shí)外，還應(yīng)能夠?qū)r(shí)間進(jìn)展調(diào)整。因此，通過模式選擇信號(hào)MOD1、MOD2控制數(shù)字鐘的工作狀態(tài)，即控制數(shù)字鐘，使其分別工作于正常計(jì)時(shí)，調(diào)整分、時(shí)和設(shè)定分、時(shí)5個(gè)狀態(tài)。當(dāng)數(shù)字鐘處于計(jì)時(shí)狀態(tài)時(shí)，3個(gè)計(jì)數(shù)器允許計(jì)數(shù)，且秒、分、時(shí)計(jì)數(shù)器的計(jì)數(shù)時(shí)鐘信號(hào)分別為CLK,秒的進(jìn)位,分的進(jìn)位;當(dāng)數(shù)字鐘處于調(diào)整時(shí)間狀態(tài)時(shí)，被調(diào)的分或時(shí)會(huì)一秒一秒地增加；當(dāng)數(shù)字鐘處于定時(shí)狀態(tài)時(shí)，可以設(shè)定小時(shí)和分；當(dāng)計(jì)時(shí)到所設(shè)定的時(shí)刻時(shí)，speak將會(huì)被賦予1KHz的脈沖信號(hào)用于驅(qū)動(dòng)揚(yáng)聲器，持續(xù)1分鐘。三、電子鐘相關(guān)功能描述如下：(1)計(jì)時(shí)功能：這是本計(jì)時(shí)器設(shè)計(jì)的根本功能，可進(jìn)展時(shí)、分、秒計(jì)時(shí)，并顯示。(2)鬧鐘功能：如果當(dāng)前時(shí)間與設(shè)置的鬧鐘時(shí)間一樣，則揚(yáng)聲器發(fā)出一段音樂，并維持一分鐘。(3)調(diào)時(shí)調(diào)分調(diào)鬧鐘功能：當(dāng)需要校時(shí)或者要重新設(shè)置鬧鐘的時(shí)間時(shí)，可通過實(shí)驗(yàn)箱上的按鍵控制。四、實(shí)現(xiàn)涉及的幾個(gè)重要模塊如下：(1)分頻器將較高速的外部時(shí)鐘頻率分頻成每分鐘一次的時(shí)鐘頻率，以便進(jìn)展時(shí)鐘計(jì)數(shù)。(2)計(jì)數(shù)器實(shí)際上是一個(gè)異步復(fù)位、異步置數(shù)的累加器，通常情況下進(jìn)展時(shí)鐘累加計(jì)數(shù)，必要時(shí)可置入新的時(shí)鐘值，然后從該值開場新的計(jì)數(shù)。(3存放器用于保存用戶設(shè)置的鬧鐘時(shí)間，是一個(gè)異步復(fù)位存放器。(4)顯示器根據(jù)需要顯示當(dāng)前時(shí)間、用戶設(shè)置的鬧鐘時(shí)間或用戶通過鍵盤輸入的新的時(shí)間，同時(shí)判斷當(dāng)前時(shí)間是否已到了鬧鐘時(shí)間，實(shí)際上是一個(gè)多路選擇器加比擬器。(5)控制器是設(shè)計(jì)的核心局部，按設(shè)計(jì)要求產(chǎn)生相應(yīng)的控制邏輯，以控制其他各局部的工作?！?〕樂曲演奏電路，實(shí)現(xiàn)鬧鐘的功能，那時(shí)間就發(fā)出一段叫“梁祝〞的樂音。實(shí)驗(yàn)代碼：1〕主程序模塊：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityszzisport(clk:instd_logic;md1:instd_logic;md2:instd_logic_vector(1downto0);speak:outstd_logic;h1,h2,m1,m2,s1,s2:outstd_logic_vector(3downto0));endszz;architectureoneofszzissignalhou1:std_logic_vector(3downto0);signalhou2:std_logic_vector(3downto0);signalmin1:std_logic_vector(3downto0);signalmin2:std_logic_vector(3downto0);signalseth1:std_logic_vector(3downto0);signalseth2:std_logic_vector(3downto0);signalsetm1:std_logic_vector(3downto0);signalsetm2:std_logic_vector(3downto0);signalsec1:std_logic_vector(3downto0);signalsec2:std_logic_vector(3downto0);begin-----------------------------------------------小時(shí)十位h110:process(clk,hou2,min1,min2,sec1,sec2,md1,md2)beginifclk'eventandclk='1'thenif(hou1="0010"andhou2="0011")and(min1="0101"andmin2="1001")and(sec1="0101"andsec2="1001")thenhou1<="0000";elsifhou1="0010"andhou2="0011"andmd1='0'andmd2="01"then--當(dāng)時(shí)間為23點(diǎn)且處于校時(shí)狀態(tài)時(shí)hou1<="0000";elsif(hou2="1001"and(min1="0101"andmin2="1001")and(sec1="0101"andsec2="1001"))or(hou2="1001"andmd1='0'andmd2="01")thenhou1<=hou1+1;endif;endif;endprocessh110;-----------------------------------------------小時(shí)個(gè)位h220:process(clk,min1,min2,sec1,sec2,md1,md2,hou1)beginifclk'eventandclk='1'thenif(hou1="0010"andhou2="0011")and(min1="0101"andmin2="1001")and(sec1="0101"andsec2="1001")thenhou2<="0000";elsifhou2="1001"and(min1="0101"andmin2="1001")and(sec1="0101"andsec2="1001")thenhou2<="0000";elsif(hou2="1001"andmd1='0'andmd2="01")or(hou1="0010"andhou2="0011")thenhou2<="0000";--md<='1';elsif((min1="0101"andmin2="1001")and(sec1="0101"andsec2="1001"))or(md1='0'andmd2="01")thenhou2<=hou2+1;--speak<=clk;endif;endif;endprocessh220;-----------------------------------------------分鐘十位m110:process(clk,min2,sec1,sec2,md1,md2)beginifclk'eventandclk='1'thenif(min1="0101"andmin2="1001")and(sec1="0101"andsec2="1001")thenmin1<="0000";elsifmin1="0101"andmin2="1001"and(md1='0'andmd2="00")thenmin1<="0000";elsif(min2="1001"and(sec1="0101"andsec2="1001"))or(min2="1001"andmd1='0'andmd2="00")thenmin1<=min1+1;endif;endif;--endif;endprocessm110;----------------------------------------------分鐘個(gè)位m220:process(clk,sec1,sec2,md1,md2)beginifclk'eventandclk='1'thenifmin2="1001"and(sec1="0101"andsec2="1001")thenmin2<="0000";elsifmin2="1001"and(md1='0'andmd2="00")thenmin2<="0000";elseif(sec1="0101"andsec2="1001")or(md1='0'andmd2="00")thenmin2<=min2+1;endif;endif;endif;endprocessm220;---------------------------------------------秒十位s110:process(clk)beginifclk'eventandclk='1'thenif(sec1="0101"andsec2="1001")thensec1<="0000";elseifsec2="1001"thensec1<=sec1+1;endif;endif;endif;endprocesss110;--------------------------------------------秒個(gè)位s220:process(clk)beginifclk'eventandclk='1'thenifsec2="1001"thensec2<="0000";elsesec2<=sec2+1;endif;endif;endprocesss220;-------------------------------------------時(shí)間設(shè)置小時(shí)局部sethour1:process(clk,seth2)beginifclk'eventandclk='1'thenifseth1="0010"andseth2="0011"thenseth1<="0000";elsifseth2="1001"thenseth1<=seth1+1;endif;endif;endprocesssethour1;------------------------------------------sethour2:process(clk,md1,md2,seth1)beginifclk'eventandclk='1'thenif(seth1="0010"andseth2="0011")orseth2="1001"thenseth2<="0000";elsifmd1='1'andmd2="00"thenseth2<=seth2+1;endif;endif;endprocesssethour2;-------------------------------------------時(shí)間設(shè)置分鐘局部setmin1:process(clk,setm2)beginifclk'eventandclk='1'thenifsetm1="0101"andsetm2="1001"thensetm1<="0000";elsifsetm2="1001"thensetm1<=setm1+1;endif;endif;endprocesssetmin1;----------------------------------------------setmin2:process(clk,md1,md2)beginifclk'eventandclk='1'thenifsetm2="1001"thensetm2<="0000";elsifmd1='1'andmd2="01"thensetm2<=setm2+1;endif;endif;endprocesssetmin2;----------------------------------------------------------------------------------------鬧鈴speaker:process(clk,hou1,hou2,min1,min2)beginifclk'eventandclk='1'thenifseth1=hou1andseth2=hou2andsetm1=min1andsetm2=min2thenspeak<=clk;elsespeak<='0';endif;endif;endprocessspeaker;--------------------------------------------------------------------------------------disp:process(md1,hou1,hou2,min1,min2,sec1,sec2,seth1,seth2,setm1,setm2)beginifmd1='0'then---------------計(jì)時(shí)時(shí)間顯示和設(shè)置模式h1<=hou1;h2<=hou2;m1<=min1;m2<=min2;s1<=sec1;s2<=sec2;else-----------鬧鈴時(shí)間現(xiàn)實(shí)和設(shè)置模式h1<=seth1;h2<=seth2;m1<=setm1;m2<=setm2;s1<="1111";s2<="1111";endif;endprocessdisp;endone;模塊一，音樂演奏電路頂層設(shè)計(jì)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYSongerISPORT(CLK12MHZ,speak:INSTD_LOGIC;CLK8HZ:INSTD_LOGIC;SPKOUT:OUTSTD_LOGIC);END;ARCHITECTUREbehavOFSongerISPONENTNoteTabsISPORT(CLK:INSTD_LOGIC;ToneInde*:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDPONENT;PONENTToneTabaISPORT(Inde*:INSTD_LOGIC_VECTOR(3DOWNTO0);Tone:OUTSTD_LOGIC_VECTOR(10DOWNTO0));ENDPONENT;PONENTSpeakeraISPORT(clk,en:INSTD_LOGIC;Tone:INSTD_LOGIC_VECTOR(10DOWNTO0);SpkS:OUTSTD_LOGIC);ENDPONENT;SIGNALTone:STD_LOGIC_VECTOR(10DOWNTO0);SIGNALToneInde*:STD_LOGIC_VECTOR(3DOWNTO0);BEGINU1:NoteTabsPORTMAP(clk=>CLK8HZ,ToneInde*=>ToneInde*);U2:ToneTabaPORTMAP(Inde*=>ToneInde*,Tone=>Tone);U3:SpeakeraPORTMAP(clk=>CLK12MHZ,Tone=>Tone,SpkS=>SPKOUT,en=>speak);END;模塊二、libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitynotetabsisport(clk:instd_logic;speak:instd_logic; toneinde*:outstd_logic_vector(3downto0));end;architectureoneofnotetabsisponentmusicport(address:instd_logic_vector(7downto0); clock:instd_logic; q:outstd_logic_vector(3downto0));endponent;signalcounter:std_logic_vector(7downto0);begin t8:process(clk,speak) begin ifcounter=138thencounter<="00000000"; elsif(clk'eventandclk='1')thenifspeak='1'thencounter<=counter+1; elsecounter<=counter; endif;endif; endprocess;u1:musicportmap(address=>counter,q=>toneinde*,clock=>clk);end; 模塊三、libraryieee;useieee.std_logic_1164.all;entitytonetabaisport(inde*:instd_logic_vector(3downto0); tone:outstd_logic_vector(10downto0));end;architectureoneoftonetabaisbegin search:process(inde*) begin caseinde*is when"0000"=>tone<="; when"0001"=>tone<="; when"0010"=>tone<="; when"0011"=>tone<="; when"0101"=>tone<="; when"0110"=>tone<="; when"0111"=>tone<="; when"1000"=>tone<="; when"1001"=>tone<="; when"1010"=>tone<="; when"1100"=>tone<="; when"1101"=>tone<="; when"1111"=>tone<="; whenothers=>null; endcase; endprocess;end;模塊四、libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityspeakerais port(clk:instd_logic; tone:instd_logic_vector(10downto0); spks:outstd_logic);endentityspeakera;architectureoneofspeakeraissignalpreclk,fullspks:std_logic;begin divideclk:process(clk) variablecount4:std_logic_vector(3downto0); begin preclk<='0'; ifcount4>11thenpreclk<='1';count4:="0000"; elsifclk'eventandclk='1'thencount4:=count4+1;