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IP屬地：天津 上傳時間：2023-02-05 格式：DOCX 頁數(shù)：8 大?。?41.02KB 積分：18 舉報 版權(quán)申訴

差分時鐘拓?fù)浞治鯬egasusYU一、 仿真條件采用差分時鐘緩沖驅(qū)動器SY100EP14作為驅(qū)動器和接收器。將IBIS模型轉(zhuǎn)為Cadence仿真的DML模型，進(jìn)行差分信號完整性的仿真(LVPEC)。模型采用3.3V供電的模型。仿真75MHz差分時鐘信號，環(huán)境為Typicalo二、 仿真過程a)PMC推薦拓?fù)銸nm1LJB?OhmRECEIVER1R]STATE100EPH3VPECLInlO^EPMJVPECLobiIOOEPH3VPLCLIflDRIVERPULSES'dWipMJOSEPHJVPECLouiSialDOnm1LJB?OhmRECEIVER1R]STATE100EPH3VPECLInlO^EPMJVPECLobiIOOEPH3VPLCLIflDRIVERPULSES'dWipMJOSEPHJVPECLouiSialDDriverEeceiverCycletlitchTol[as]FTSModetlitchMonotonicHoiseXarein[-T]OvershootHich.[-T]OvershootL[■T]1DESItH.DRIVER.1DESICH.RECEIVER.13200.01056TypPASSFAIL-485.172583.29737.4731DESIGN.DRIVER.2DESIGH.RECEIVER.14200.01056TypPASSPASSNANAHADESIGN.DRIVER.1DESIGNRECEIVER.13_DESICN.RECEIVER.14_diff200.0105BTypFAILFAIL-432.5492385.67-997.66BJDODD300DESIGNRECEIVER13_DESIGNRECEIVER14_diffb)USI推薦拓?fù)銬ESIGNRECEIVER13_DE.SIGNRECE.IWR14_diffc)EMC推薦拓?fù)?DESIGNRECEIWR13_DE.SIGNRECEIVER.14_diff三、分析及改進(jìn)很顯然，上面的三種波形，都不滿足時鐘信號單調(diào)性的要求。EMC的設(shè)計，由于不正確的偏置，導(dǎo)致輸入電壓擺幅過大°USI的設(shè)計，沒有加電源和地之間的電容，對電源平面受到的干擾考慮不足。將PMC的設(shè)計中，串接AC電容的容值改為1uf，見下圖仿真波形，沒有波形的優(yōu)良改善。單調(diào)性仍然不過

r caseU-MonJm2111」二:心:41NLll」苫j iiiiIiiiiIiiiiIiir DESIGNRECEIVER13DESIGNRECEIVER14cliff上面PMC推薦的拓?fù)?，是?jù)同事所說，PMC有這樣串接AC電容的連接方式。根據(jù)打印出來的PMC差分時鐘設(shè)計部分原理圖，從晶振到時鐘驅(qū)動芯片，沒有串接AC電容。從晶振的datasheet上看，也沒有推薦使用AC串接電容。所以，下面采用不串接AC耦合電容的拓?fù)?。JODOO1LW；ibIDDriverDESIGN.DRIVER.1HESIGIT.DRIVER.2HESIGIT.RECEIVER.13DESIGN.RECEIVER.14tlitchTol[心]0.010560.01056FTSModetlitchPASSPASSMonoton!cFAILFAIL-709.46-709.49Otersh.001Hieh.3059.233059.23Otersh.001Low[■刁1211.071209.66PropDelay[ns]DESIGN.DRIVER.1HESIGIT.RECEIVER.1J?I的EP14JODOO1LW；ibIDDriverDESIGN.DRIVER.1HESIGIT.DRIVER.2HESIGIT.RECEIVER.13DESIGN.RECEIVER.14tlitchTol[心]0.010560.01056FTSModetlitchPASSPASSMonoton!cFAILFAIL-709.46-709.49Otersh.001Hieh.3059.233059.23Otersh.001Low[■刁1211.071209.66PropDelay[ns]DESIGN.DRIVER.1HESIGIT.RECEIVER.1J?I的EP14胛PLCLinRECEIVERTEME.ii：「1DCkpMJ0DLPJ4_jy_PELlinjj:_DE20Q.Q1056|TfdFASSFASS 3T6 1695.38DRIVERPULSEij-JOOrpMIDuLPHJVPLCLuulK1DOLPHJVPLCLnul■-RM:-BfhDhm-F?5-RL5OhmDLJHICHK1RIPmoOhnDL2p^mtipipJODOhm>P3：-J-JDOhm DEWIGERECEIVER13_DESIGNRECE.IWR14_diff很顯然，去除AC耦合電容后，波形得到改善，接收到的時鐘信號已滿足單調(diào)性要求。因此，應(yīng)采用PMC推薦設(shè)計（不串接AC耦合電容）。可以看到，上面的波形仍然存在塌陷，屬于不良的波形，仍然有可能影響單調(diào)性。因此，需要繼續(xù)進(jìn)行改進(jìn)。之前的偏置上下拉部分，是放在靠近驅(qū)動器的一端。根據(jù)經(jīng)驗，放在接收器一邊將會更好的吸收反射。改進(jìn)的拓?fù)洌篔QQDQ[■IDDESIGN.DRIVER.1HESIGN.DRIVER.2DESIGN.DRIVER.1DESIGN.RECEIVER.13DESItlT.FLECEIVER.14DESIGN.RECEIVER.13tlitchTol0.010560.010560.01056FTSXodetlitchPASSFAILPASSMonoton!cFAILFAILPASSHoiseMarein頃]-868.15692.663OTershootHieh2471.991136.02OvershootLow頃]1237.821237.77-1134.92PropDelayg]1.51.51.5SwitchBelay-1.68664-1.689891.88488DRIVERPUL$EE.yJGDEpMItiOLPHJVJ'ECLriulDL1MJMfiiPJPJ00anrviDL3MIDVH-IPIPJQDOnfTiDL2UI-TFObiPIPJODDEJQQDQ[■IDDESIGN.DRIVER.1HESIGN.DRIVER.2DESIGN.DRIVER.1DESIGN.RECEIVER.13DESItlT.FLECEIVER.14DESIGN.RECEIVER.13tlitchTol0.010560.010560.01056FTSXodetlitchPASSFAILPASSMonoton!cFAILFAILPASSHoiseMarein頃]-868.15692.663OTershootHieh2471.991136.02OvershootLow頃]1237.821237.77-1134.92PropDelayg]1.51.51.5SwitchBelay-1.68664-1.689891.88488DRIVERPUL$EE.yJGDEpMItiOLPHJVJ'ECLriulDL1MJMfiiPJPJ00anrviDL3MIDVH-IPIPJQDOnfTiDL2UI-TFObiPIPJODDEJO&LPJJIVPECLinItlOLPIW'ECLriulRECEIVERTRJSltUE：r1b知14—J*IUOEPltJV_F-LCLincaseU-MemJan2111:1!?:2U20080 100 200 300Tiiiie[ns]DESIGNRECEIW.R13_DESIGNRECEIW.R14_diff很明顯，波形已得到很好的改善。對于時鐘信號邊沿的單調(diào)性要求，已達(dá)到要求。并且電平部分的過沖也得到控制。四、結(jié)論1）采用下圖的拓?fù)浞绞竭B接差分時鐘信號（即PMC的推薦）ClIcoonpF10OLPI<^_PECLnu1IDOEPUJVLCLinJOODOpF&?.&OhmDL1pjmfiipjpJ00OhmDL3Hirra-ipipJODOhmDL2HI-UObiPIFJODOhmDRIVERPULSEE.yJ'3DEpMItluLPN山,PECLod旺CE1VERTRjmTES—OOepMJOC-EPJJIVPECLinD]R]收器tchBelay0 100 200 300Tiiiie[ns]DESIGNRECEIW.R13_DESIGNRECEIW.R14_diff很明顯，波形已得到很好的改善。對于時鐘信號邊沿的單調(diào)性要求，已達(dá)到要求。并且電平部分的過沖也得到控制。四、結(jié)論1）采用下圖的拓?fù)浞绞竭B接差分時鐘信號（即PMC的推薦）ClIcoonpF10OLPI<^_PECLnu1IDOEPUJVLCLinJOODOpF&?.&OhmDL1pjmfiipjpJ00OhmDL3Hirra-ipipJODOhmDL2HI-UObiPIFJODOhmDRIVERPULSEE.yJ'3DEpMItluLPN山,PECLod旺CE1VERTRjmTES—OOepMJOC-EPJJIVPECLinD]R]收器tchBelay[ns]0.0105BITzdFAILFAIL-868.15NA1237.771.5-1.68989ir/M，歐％51136.02-1134.321.51.884882471.99-1.686640.01056TypPASSFAIL1237.821.5五、進(jìn)一步驗證Fast和Slow是兩種極限仿真條件。如果在這兩種條件下，時鐘能夠滿足信號完整性要求，那么實際的信號就不會出問題。即便不能滿足Fast和Slow條件，只要typical條件下足夠好，實際情況下，出問題的概論會很小。SialDDriverEeceiverCtcIetlitchTol[ns]FTSModetlitchMonotonicHoiseMar[-T]1DESIGN.DRIVER.2DESIGN.RECEIVER.145一0.007771SlowPASSPASSNA2__1DESIGN.DRIVER.1DESIGN.RECEIVER.13_DESI&1T.RECEIVER.[50.007771SlowPASSPASS33.5343DESIGN.DRIVER.1DESIGN.FlECEIVER.1350.012224FastPASSFAIL31.1431.12DESIGN.DRIVER.2DESIGN.RECEIVER.1450.012224FastPASSFAIL土 1DESIGN.DRIVER.1DESIGN.RECEIVER.13_DESIC1T.RECEIVER.14_diff[50.012224FastPASSPASS123.7393DESIGN.DRIVER.1DESIGN.RECEIVER.1350.01056TfpPASSFAIL-65.39-S6S.