數(shù)字電路與邏輯設(shè)計(jì) 基于VHDL的數(shù)字邏輯設(shè)計(jì)2

基于VHDL的數(shù)字邏輯設(shè)計(jì)時(shí)序邏輯部分二、常用時(shí)序邏輯電路設(shè)計(jì)（1）觸發(fā)器設(shè)計(jì)（D）（2）計(jì)數(shù)器設(shè)計(jì)（分頻器）（3）移位寄存器設(shè)計(jì)（4）狀態(tài)機(jī)設(shè)計(jì)：序列檢測(cè)器

（1）觸發(fā)器設(shè)計(jì)DQCPCPDQn+1無(wú)變化XQn0->1000->111D觸發(fā)器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYdffISPORT(cp,d:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDdff;ARCHITECTUREaOFdffISBEGINprocess(cp)beginifcp'eventandcp='1'thenq<=d;endif;endprocess;ENDa;(2)-A簡(jiǎn)單計(jì)數(shù)器設(shè)計(jì)計(jì)數(shù)器CLKQ3Q2Q1Q0四位加計(jì)數(shù)器LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk:inSTD_LOGIC;q:buffer

STD_LOGIC_vector(3downto0));ENDcounter;ARCHITECTUREaOFcounterISBEGIN

process(clk)

begin

if(clk'eventandclk='1')thenq<=q+1;

endif;

endprocess;ENDa;四位加計(jì)數(shù)器計(jì)數(shù)器CLKCLR(2)-B帶同步清零、同步置數(shù)功能的計(jì)數(shù)器LDQ3Q2Q1Q0D3D2D1D0控制信號(hào)CLR、LD：具有更高優(yōu)先級(jí)LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk,clr,ld:inSTD_LOGIC;d:inSTD_LOGIC_vector(3downto0);q:bufferSTD_LOGIC_vector(3downto0));ENDcounter;ARCHITECTUREaOFcounterISBEGIN

process(clk)

begin

if(clk'eventandclk='1')thenif(clr='1')then

q<="0000";elsif(ld='1')thenq<=d;

elseq<=q+1;

endif;endif;endprocess;ENDa;計(jì)數(shù)器CLKCLR(2)-C帶異步清零、同步置數(shù)功能的計(jì)數(shù)器LDQ3Q2Q1Q0D3D2D1D0LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk,clr,ld:inSTD_LOGIC;d:inSTD_LOGIC_vector(3downto0);q:bufferSTD_LOGIC_vector(3downto0));ENDcounter;ARCHITECTUREaOFcounterISBEGIN

process(clk,clr)begin

if(clr=‘1’)thenq<=“0000”;

else

if(clk'eventandclk='1‘)

thenif(ld='1')then

q<=d;

elseq<=q+1;

endif;

endif;endif;

endprocess;ENDa;(2)-D帶進(jìn)位計(jì)數(shù)器設(shè)計(jì)計(jì)數(shù)器CLKQ3Q2Q1Q0四位加計(jì)數(shù)器COUTLIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;USEieee.std_logic_arith.ALL;ENTITYcounterISPORT(clk:inSTD_LOGIC;q:buffer

STD_LOGIC_vector(3downto0);cout:outstd_logic);ENDcounter;ARCHITECTUREaOFcounterISBEGINprocess(clk) variabletmp:std_logic_vector(3downto0);begin

if(clk'eventandclk='1')thenq<=q+1;tmp:=q+1;

if(tmp=15)thencout<='1';

elsecout<='0';

endif;

endif;endprocess;ENDa;(3)分頻器設(shè)計(jì)Tclk=1usTcout=10us計(jì)數(shù)器就是對(duì)時(shí)鐘脈沖計(jì)數(shù)，同時(shí)計(jì)數(shù)器還是一個(gè)分頻器。（4）移位寄存器設(shè)計(jì)4位右移移位寄存器Reset:異步清零右移移位寄存器dinresetclkQAQBQCQDlibraryieee;useieee.std_logic_1164.all;ENTITYshifterISPORT(

din:instd_logic;reset,clk:instd_logic;QA,QB,QC,QD:bufferstd_logic);

ENDshifter;ARCHITECTUREbehaveOFshifterISBEGINProcess(reset,clk)Begin

if(reset='1')

then

QA<='0';QB<='0';QC<='0