數(shù)電實(shí)驗(yàn)報(bào)告 vhdl 微波爐fpga分模塊實(shí)現(xiàn)

1、數(shù)電綜合實(shí)驗(yàn)報(bào)告-簡(jiǎn)易微波爐控制器的設(shè)計(jì)與實(shí)現(xiàn)1一：設(shè)計(jì)課題的任務(wù)要求- 3二：系統(tǒng)設(shè)計(jì)（包括設(shè)計(jì)思路、總體框圖、分塊設(shè)計(jì)）- 33441 253：控制器464-76-8798 9三：仿真波形及波形分析- 1112 3 56 78 四：源程序- 151：分頻器2 3：控制器 59 五：功能說(shuō)明- 33六：元件清單和利用情況- 33七：故障和問(wèn)題分析- 33八：總結(jié)和結(jié)論- 342基本要求：1、2、分 43、4、5、6、提高要求：1、用 8個(gè) 8個(gè)2、3、4、設(shè)計(jì)思路 為13：防抖模塊左邊為時(shí)間輸入防抖，右邊為火力輸入和開(kāi)始鍵的防抖。：控制器狀態(tài)控制器的功能根據(jù)輸入信號(hào)和自身當(dāng)時(shí)所處的狀態(tài)完成狀

2、態(tài)的轉(zhuǎn)換和輸出相應(yīng)的控制信號(hào)，其模塊框圖如圖所示。其中，輸出信號(hào)LD_DONE 指示數(shù)據(jù)裝載電路載入的烹調(diào)結(jié)束的狀態(tài)信息的顯示的驅(qū)動(dòng)信息數(shù)據(jù)；LD_CLK 顯示數(shù)據(jù)裝載電路的設(shè)置的時(shí)間數(shù)據(jù)；LD_EDIT 用于輸出給其他分模塊以便設(shè)置是否可改變；COOK 指示烹飪的狀態(tài)，并提示計(jì)時(shí)器進(jìn)行減法計(jì)算；DATA15.0：將 key 轉(zhuǎn)化為二進(jìn)制編碼；KEY 為定時(shí)時(shí)間輸入信號(hào)，用于設(shè)置烹飪時(shí)間的長(zhǎng)短，其高到低分別表示時(shí)間分、秒的十位、個(gè)位。當(dāng) LD_DONE 有效時(shí)，輸出烹調(diào)結(jié)束數(shù)據(jù)。當(dāng) LD_CLK 有效時(shí)，輸出烹調(diào)的設(shè)置時(shí)間數(shù)據(jù)。5：數(shù)據(jù)裝載當(dāng)LD_DONEL_CLK烹調(diào)的設(shè)置時(shí)間數(shù)據(jù)。由于結(jié)構(gòu)

3、內(nèi)部用到與或表達(dá)式LOADqqqqqqqq=10000000;的循環(huán)。Dianzhenlieshuju 是每列對(duì)應(yīng)的數(shù)據(jù)，用于完成大中小三個(gè)字的顯示。低電平有效。9：led 顯示模塊Clk 外接 1hz 分頻，用于內(nèi)部對(duì)秒的計(jì)數(shù)。Key 接受輸入的時(shí)間信號(hào)，并在內(nèi)部轉(zhuǎn)化成秒數(shù)。對(duì)clk的計(jì)數(shù)和key 1/8,2/8,3/87/8個(gè)key時(shí)點(diǎn)亮相應(yīng)的 led 燈。Ledbar用于輸出led顯示信號(hào)從00000000-11111111.clk沒(méi)到達(dá)一定數(shù)字，相應(yīng)的增加一位 1 顯示。計(jì)數(shù)完成時(shí)，led 全部點(diǎn)亮。Set 用于清空 clk 計(jì)數(shù)。Start 用于將 key 的輸入轉(zhuǎn)化成秒數(shù)。：蜂鳴器

4、模塊21010總框圖11：控制器仿真 開(kāi)始計(jì)時(shí)，COOK 正在烹飪,Key 輸入 59 分 00 秒。Start 按之前，ld_clk 為有效，可改變數(shù)碼管顯示，start 按下后 ld-clk 為 0，不能改變，同時(shí) ld-edit 變?yōu)榈碗娖剑刂破渌K不可改變，同時(shí) cook 信號(hào)變?yōu)?1，表示開(kāi)始倒計(jì)時(shí)。Reset 后 DATA 變回 0.2數(shù)據(jù)裝載仿真號(hào)123倒計(jì)時(shí)模塊：圖中，LOAD 為高電平時(shí)讀取信號(hào) DATA 的值，當(dāng) COOK 信號(hào)為高電平時(shí)，對(duì)DATA 的值進(jìn)行減法計(jì)數(shù)，并在每個(gè)時(shí)鐘周期都輸出減法計(jì)數(shù)器的當(dāng)前值。仿真結(jié)果與預(yù)先設(shè)定的電路功能相吻合。4:decoder譯碼電

5、路模塊013：驅(qū)動(dòng)數(shù)碼管模塊可見(jiàn) a 輪流顯示每個(gè)數(shù)碼管T 則相應(yīng)的數(shù)碼管上顯示相應(yīng)的數(shù)字。符合預(yù)期。：led 顯示模塊Key 輸入 11 秒在 start 后 11 秒左右，ledbar 全部為 1，完成 led 功能。且 reset 后 ledbar清零。：蜂鳴器模塊214：總體仿真1：分頻器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpinqi1hz isport(clk_in : in std_logic;clk_out : out std_logic);end;a

6、rchitecture a of fenpinqi1hz issignal cnt : integer range 0 to 24999999; -用于clk 10khz 為 2499，100hz 為 249999）signal clk_tmp : std_logic;beginprocess(clk_in)beginif (clk_inevent and clk_in=1) thenif cnt=24999999 thencnt=0;clk_tmp= not clk_tmp;-輸出相反電平elsecnt=cnt+1;end if;end if;end process;clk_out=clk_

7、tmp;end;152：防抖模塊LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity fangdou isport (CLK_100hz:in std_logic;-定義端口key:in std_logic_vector(3 downto 0); -按鍵輸入keyout:out std_logic_vector(3 downto 0) -按鍵輸出);end fangdou;architecture art of fangdou is

8、signal tmp1:std_logic_vector(3 downto 0);signal tmp2:std_logic_vector(3 downto 0);beginPROCESS(CLK_100hz,key)BEGINIF(CLK_100hzevent AND CLK_100hz=0)THEN消抖部分tmp2(0)=tmp1(0);tmp1(0)=key(0);tmp2(1)=tmp1(1);tmp1(1)=key(1);tmp2(2)=tmp1(2);tmp1(2)=key(2);tmp2(3)=tmp1(3);tmp1(3)=key(3);END IF;keyout(0)= CL

9、K_100hz AND tmp1(0) AND (NOT tmp2(0);keyout(1) =CLK_100hz AND tmp1(1) AND (NOT tmp2(1);keyout(2) =CLK_100hz AND tmp1(2) AND (NOT tmp2(2);keyout(3) =CLK_100hz AND tmp1(3) AND (NOT tmp2(3);END PROCESS;end art;3：控制器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LO

10、GIC_ARITH.ALL;16ENTITY controller ISPORT(RESET:IN STD_LOGIC;-復(fù)位KEY: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -鍵盤(pán)時(shí)間輸入START:IN STD_LOGIC;-開(kāi)始鍵CLK:IN STD_LOGIC;-1hz 輸入-完成信號(hào)DONE:IN STD_LOGIC;COOK:OUT STD_LOGIC;LD_CLK:OUT STD_LOGIC;-將 key載入作為時(shí)間信號(hào)DATA:OUT STD_LOGIC_VECTOR(15 DOWNTO 轉(zhuǎn)換后的輸出LD_DONE:OUT STD_LOGIC;LD_E

11、DIT:OUT STD_LOGIC-完成輸出);END controller;ARCHITECTURE rtl OF controller ISTYPE STATES IS(IDLE,SET_CLOCK,TIMER,DONE_MSG);SIGNAL NXT,CUR:STATES; 兩個(gè)狀態(tài)，當(dāng)前和下一個(gè)SIGNAL DATATMP:STD_LOGIC_VECTOR(15 DOWNTO 0);SIGNAL EDIT:STD_LOGIC;-signal startn:std_logic:=0;BEGINPROCESS(CLK,RESET)BEGIN時(shí)鐘和復(fù)位進(jìn)程IF RESET=1 THENCUR

12、=IDLE;-復(fù)位時(shí)將 IDLE（顯示 ）賦予當(dāng)前狀態(tài)ELSIF CLKEVENT AND CLK=1 THENCUR=NXT; -如果不是，遇到上邊沿則自動(dòng)跳轉(zhuǎn)下一狀態(tài)END IF;END PROCESS;PROCESS(RESET,KEY)BEGIN復(fù)位和輸入的進(jìn)程-可以讓輸入4 位數(shù)字 顯示時(shí)間-復(fù)位時(shí)不論任何狀態(tài)數(shù)碼管都將顯示0000IF RESET = 1 THENDATATMP 0);ELSEIF KEY(3)EVENT AND KEY(3) = 1 THEN-設(shè)置分的十位IF DATATMP(15 DOWNTO 12) = 0101 自動(dòng)跳轉(zhuǎn)到0DATATMP(15 DOWNTO

13、 12) = 0000;ELSE17DATATMP(15 DOWNTO 12) = DATATMP(15 DOWNTO 12) + 1;END IF; -否則自動(dòng)加1END IF;IF KEY(2)EVENT AND KEY(2) = 1 THEN-設(shè)置分的個(gè)位IF DATATMP(11 DOWNTO 8) = 1001 THEN -9 自動(dòng)跳轉(zhuǎn)到0DATATMP(11 DOWNTO 8) = 0000;ELSEDATATMP(11 DOWNTO 8) = DATATMP(11 DOWNTO 8) + 1;END IF;END IF;否則自動(dòng)加1IF KEY(1)EVENT AND KEY(1

14、) = 1 THENIF DATATMP(7 DOWNTO 4) = 0101 THENDATATMP(7 DOWNTO 4) = 0000;ELSE-設(shè)置秒的十位-5 自動(dòng)跳轉(zhuǎn)到0DATATMP(7 DOWNTO 4) = DATATMP(7 DOWNTO 4) + 1;END IF; 否則自動(dòng)加1END IF;IF KEY(0)EVENT AND KEY(0) = 1 THEN-設(shè)置秒的個(gè)位-9 自動(dòng)跳轉(zhuǎn)到0IF DATATMP(3 DOWNTO 0) = 1001 THENDATATMP(3 DOWNTO 0) = 0000;ELSEDATATMP(3 DOWNTO 0) = DATAT

15、MP(3 DOWNTO 0) + 1;END IF;END IF;END IF;-否則自動(dòng)加1DATA = DATATMP;END PROCESS;PROCESS(START,RESET)BEGIN-IF RESET = 1 THENEDIT = 1;-將 edit 置 1ELSIF STARTEVENT AND START = 1 THEN -如何start按下將 edit 置 0EDIT = 0;END IF;END PROCESS;PROCESS(CLK,CUR,EDIT,DONE) ISBEGINNXT=IDLE;-將 IDLE 載入 NXT- LD_POWER=0;LD_DONE=0

16、;LD_CLK=0;-COOKLD_CLK=1;-烹調(diào)時(shí)間測(cè)試狀態(tài)COOKLD_DONE=0;COOKIF EDIT=1 THENNXT=SET_CLOCK;LD_CLK=1;ELSIF DONE=0 THENNXT=TIMER;COOKIF DONE=1 THENNXT=DONE_MSG;LD_DONE=0;cook=0;-設(shè)置計(jì)時(shí)完成ELSENXT=TIMER;COOKNULL;END CASE;END PROCESS;PROCESS(EDIT) ISBEGINLD_EDIT=EDIT;END PROCESS;END rtl;4:數(shù)據(jù)裝載模塊LIBRARY IEEE;USE IEEE.ST

17、D_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY loader IS19PORT(DATAIN:IN STD_LOGIC_VECTOR(15 DOWNTO 輸入 16 位數(shù)據(jù)LD_TEST:IN STD_LOGIC;LD_CLK:IN STD_LOGIC;LD_DONE:IN STD_LOGIC;DATAOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 輸出16 位數(shù)據(jù)LOAD:OUT STD_LOGIC-選擇狀態(tài));END loader;ARCHITECTURE rtl OF loader ISBEGINPROCES

18、S(DATAIN,LD_TEST,LD_CLK,LD_DONE)CONSTANT ALLS:STD_LOGIC_VECTOR(15 DOWNTO 測(cè)試信息:=1000100010001000; -顯示8888CONSTANT DONE:STD_LOGIC_VECTOR(15 DOWNTO 烹調(diào)完成信息:=1010101111001101;VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINLOAD-烹調(diào)完成DATAOUTDATAOUTNULL;END CASE;END PROCESS;END rtl;5：倒計(jì)時(shí)模塊1：十進(jìn)制計(jì)數(shù)器LIBRARY IE

19、EE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY cnt10 ISPORT(CLK:IN STD_LOGIC;LOAD,CLR:IN STD_LOGIC;EN:IN STD_LOGIC;-CLR：清除數(shù)據(jù)-信號(hào)使能20DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 輸入的4 位數(shù)據(jù)Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CARRY_OUT:OUT STD_LOGIC-輸出的4 位數(shù)據(jù)-數(shù)據(jù)裝載);END cnt10;ARCHITECTURE rtl O

20、F cnt10 ISSIGNAL TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);-鏈接輸入輸出BEGIN -數(shù)據(jù)的信號(hào)PROCESS(CLK,LOAD,CLR,EN)BEGINIF CLR = 1 THEN-當(dāng) CLR 高電平，數(shù)據(jù)變?yōu)?000TMP= 0000;ELSIF LOAD=1THENTMP=DATAIN;-否則裝載輸入的數(shù)據(jù)ELSIF CLKEVENT AND CLK=0THEN -上升沿時(shí)，執(zhí)行 10 進(jìn)制減法IF EN=1THENIF TMP=0000THENTMP=1001;ELSE-0 跳轉(zhuǎn)到 9-自動(dòng)減 1TMP=TMP-1;END IF;END IF

21、;END IF;IF TMP=0000THENCARRY_OUT=1;-COOK=CARRY_OUTELSECARRY_OUT=0;END IF;END PROCESS;Q=TMP;END rtl;2：-六進(jìn)制減法計(jì)數(shù)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY cnt6 ISPORT(CLK:IN STD_LOGIC;LOAD,CLR:IN STD_LOGIC;21EN:IN STD_LOGIC;DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);Q:

22、OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CARRY_OUT:OUT STD_LOGIC);END cnt6;ARCHITECTURE rtl OF cnt6 ISSIGNAL TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,LOAD,CLR,EN)BEGINIF CLR = 1 THENTMP= 0000;ELSIF LOAD=1 THENTMP=DATAIN;ELSIF CLKEVENT AND CLK=0THENIF EN=1THENIF TMP=0000THENTMP=0101;ELSE-上升沿時(shí)進(jìn)行 6 進(jìn)制

23、減法-0 自動(dòng)跳轉(zhuǎn)到5-否則自動(dòng)減1TMP=TMP-1;END IF;END IF;END IF;IF TMP=0000THENCARRY_OUT=1;ELSE-賦值給COOKCARRY_OUT=0;END IF;END PROCESS;Q=TMP;END rtl;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;3:總的計(jì)數(shù)器ENTITY counter ISPORT(COOK:IN STD_LOGIC;LOAD,CLR:IN STD_LOGIC;22CLK:IN STD_LOGIC;DATA:IN STD_LOGIC_VECTOR(15 DOWNTO 0);

24、SEC0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -秒個(gè)位SEC1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -秒十位MIN0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -分個(gè)位MIN1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -分十位DONE:OUT STD_LOGIC-完成);END counter;ARCHITECTURE rtl OF counter IS-定義十進(jìn)制和六進(jìn)制計(jì)數(shù)器電路模塊COMPONENT cnt10 ISPORT(CLK:IN STD_LOGIC;LOAD,C

25、LR:IN STD_LOGIC;EN:IN STD_LOGIC;DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); -輸入Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CARRY_OUT:OUT STD_LOGIC-輸出-狀態(tài));END COMPONENT cnt10;COMPONENT cnt6 ISPORT(CLK:IN STD_LOGIC;LOAD,CLR:IN STD_LOGIC;EN:IN STD_LOGIC;DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);Q:OUT STD_LOGIC_VECTOR(

26、3 DOWNTO 0);CARRY_OUT:OUT STD_LOGIC);END COMPONENT cnt6;SIGNAL CLK0:STD_LOGIC;SIGNAL S0:STD_LOGIC;SIGNAL S1:STD_LOGIC;SIGNAL S2:STD_LOGIC;SIGNAL S3:STD_LOGIC;BEGIN-元件例化CLK0 = NOT CLK;U1:cnt10 PORT MAP(CLK0,LOAD,CLR,COOK,DATA(3 DOWNTO 0),SEC0,S0);U2:cnt6 PORT MAP(S0,LOAD,CLR,COOK,DATA(7 DOWNTO 4),SEC

27、1,S1);23U3:cnt10 PORT MAP(S1,LOAD,CLR,COOK,DATA(11 DOWNTO 8),MIN0,S2);U4:cnt6 PORT MAP(S2,LOAD,CLR,COOK,DATA(15 DOWNTO 12),MIN1,S3);DONE DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 DOUT7 = 0000000;END CASE;END PROCESS;END ARCHITECTURE ART;8：數(shù)碼管驅(qū)動(dòng)電路LIBRARY IEEE

28、;USE IEEE.STD_LOGIC_1164.ALL;24use ieee.std_logic_unsigned.all;ENTITY qudong ISPORT (clk: In std_logic;t1 : in std_logic_vector(6 DOWNTO 0); - sec0 輸入t2: in std_logic_vector(6 DOWNTO 0);-sec1 輸入t3 : in std_logic_vector(6 DOWNTO 輸入t4: in std_logic_vector(6 DOWNTO 輸入t5:in std_logic;edit:in std_logic;t

29、: out std_logic_vector(6 DOWNTO 輸出a:OUT STD_LOGIC_vector(5 DOWNTO 選擇數(shù)碼管);END qudong;ARCHITECTURE arch OF qudong ISSIGNAL n: std_logic_vector(2 DOWNTO 0);signal t_temp2:std_logic:=1;signal t_temp:std_logic_vector(6 downto 0);signal a_temp:std_logic_vector(5 downto 0);BEGINprocess(edit,t5)beginif(edit

30、=1) thenif(t5event and t5=1) thent_temp2=not t_temp2;end if;end if;end process;PROCESS(clk,t_temp2)BEGINIF(clkevent and clk=1) THENIF (n=000 ) THENt_temp = t1;a_temp=111110;n = n+1;ELSif(n=001) thent_temp = t2;a_temp=111101;25n =n+1 ;elsif(n=010) thent_temp=t3;a_temp=111011;n=n+1;elsif(n=011) thent_

31、temp=t4;a_temp=110111;n=n+1;elsif(n=100) thena_temp=011111;if(t_temp2=0)thent_temp=0111111;elset_temp=0000110;end if;n=000;END IF;END IF;END PROCESS ;t=t_temp;a=a_temp;END arch;9：火力模塊1：點(diǎn)陣計(jì)數(shù)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dianzhenjishu isport(power:in s

32、td_logic;reset:in std_logic;edit:in std_logic;q:out std_logic_vector(1 downto 0);end dianzhenjishu;ARCHITECTURE COUNT OF dianzhenjishu issignal q_temp:std_logic_vector(1 downto 0);beginprocess(power,reset,edit)beginif (reset=1) then26q_temp=00;elsif(edit=1) thenif(power event and power=1)thenif q_te

33、mp =10 thenq_temp=00;elseq_temp=q_temp+1;end if;end if;end if;end process;q=q_temp;end COUNT;2:點(diǎn)陣列選擇library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity DIANZHENXUANZELIE isport( clk: in std_logic;reset: in std_logic;q: out std_logic_vector(7 downto 0);end DIANZHENXUANZELI

34、E;architecture cnt_arc of DIANZHENXUANZELIE issignal n:INTEGER RANGE 0 TO 7;beginprocess (clk)beginif clkevent and clk=1 thenif n= 7 then n=0;elsenqqqqqqqqqCASE sel ISWHEN 00000001 = q q q q q q q q NULL;END CASE;WHEN 01 =CASE sel ISWHEN 00000001 = q q q q q q q q NULL;END CASE;WHEN 10 =CASE sel ISW

35、HEN 00000001 = q q q q q q q q NULL;END CASE;WHEN OTHERS = NULL;END CASE;END PROCESS;END corn_arc;10：led 模塊LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_lOGIC_ARITH.ALL;USE IEEE.NUMERIC_STD.ALL;entity ledbar isport(clk:in std_logic;reset:in std_logic;start:in std_logic;key:in std_logic_vecto

36、r(3 downto 0);-total2:out integer range 0 to 3600;-now2:out integer range 0 to 3600;ledbar:out std_logic_vector(7 downto 0);end ledbar;architecture art1 of ledbar issignal min1:integer range 0 to 5;29signal min0:integer range 0 to 9;signal sec1:integer range 0 to 5;signal sec0:integer range 0 to 9;s

37、ignal totals:integer range 0 to 3600;signal nows:integer range 0 to 3600;signal startn:std_logic:=0;-signal reset1:std_logic:=0;beginprocess(key,reset,min1,min0,sec1,sec0)beginif(reset=1) thenmin1=0;min0=0;sec1=0;sec0=0;elseif(key(3)event and key(3)=1) thenif(min1=5)thenmin1=0;elsemin1=min1+1;end if

38、;end if;if(key(2)event and key(2)=1) thenif(min0=9)thenmin0=0;elsemin0=min0+1;end if;end if;if(key(1)event and key(1)=1) thenif(sec1=5)thensec1=0;elsesec1=sec1+1;end if;end if;if(key(0)event and key(0)=1) thenif(sec0=9)thensec0=0;elsesec0=sec0+1;end if;30end if;end if;end process;process(start,reset

39、,totals)beginif(reset=1)thenstartn=0;elsif(startevent and start=1) then-totals=(min1(3)*8+min1(2)*4+min1(1)*2+min1(0)*1)*10*60+(min0(3)*8+min0(2)*4+min0(1)*2+min0(0)*1)*60+(sec1(3)*8+sec1(2)*4+sec1(1)*2+sec1(0)*1)*10+(sec0(3)*8+sec0(2)*4+sec0(1)*2+sec0(0)*1);totals=min1*10*60+min0*60+sec1*10+sec0;startn=1;end if;-total2=totals;end process;process(clk,startn,reset,totals,nows)beginif reset=1 thennows=0;elsif(startn=1) thenif(clkevent and clk=1) thennows=nows+1;end if;end if;-now2=nows;if (now