2013《數(shù)字邏輯設(shè)計》期末考試-試題及參考答案

1、學(xué)院姓名學(xué)號任課老師考場教室_選課號/座位號密封線以內(nèi)答題無效 2012 -2013 二 末 A 卷課程名稱：_數(shù)字邏輯設(shè)計及應(yīng)用_ 考試形式： 閉卷考試時長：_120_分鐘考試日期：20 13 年 07 月 05 日課程成績構(gòu)成：平時 30 % ， 期中 30 % ， 實(shí)驗(yàn)本試卷試題由_七_(dá)部分構(gòu)成，共_7_頁。0%， 期末 40 %題號得分合計得 分I. Fill out your answers in the blanks (3 X 10=30)1. If a 74x138 binary decoder has 110 on its inputs CBA,the active LOW o

2、utput Y5 should be ( 1 or high ).2. If the next state of the unused states are marked as “dont-cares” when designing a finite state machine, thisapproach is called minimal ( cost ) approach.3.The RCO_L of 4-bit counter 74x169 is ( 0 or low) when counting to 0000 in decreasing order.To design a 00101

3、0 serial sequence generator by shift registers, the shift register should need4.( 4 ) bitatleast.5. One state transition equation is Q* = JQ+KQ. If we use T flip-flop with enable to complete the equation，the enable input of T flip-flop should have the function EN = (JQ+KQ ). （參見課件 Flip-flopsTransfor

4、ming Skills.ppt）6. A 4-bit Binary counter can have (16 ) normal states at most, 4-bit Johnson counter with nonormal states, 4-bit linear feedback shift-register (LFSR) counter withnormalstates.self-correction can have (self-correction can have (8 )16 )If we use a ROM, whose capacity is 16 4 bits, to

5、 construct a 4-bit binary code to gray code7.converter, when the address inputs are 1001, ( 1101 ) will be the output.8. When the input is 10000000 of an 8 bit DAC,the corresponding output voltage is 2V. The output voltage is第 1 頁 共 7 頁學(xué)院姓名學(xué)號任課老師考場教室_選課號/座位號密封線以內(nèi)答題無效(3.98) V when the input is 111111

6、11.得 分II. Please select the only one correct answer in the following questions.(2 X 5=1. If a 74x85 magnitude comparator has ALTBIN=1, AGTBIN=0,AEQBIN=0,A3A2A1A0=1101,B3B2B1B0=0111 on its inputs, the outputs are ( D ).A)ALTBOUT=0,AEQBOUT=0,AGTBOUT=0C) ALTBOUT=1,AEQBOUT=0,AGTBOUT=1B) ALTBOUT=1,AEQBOU

7、T=0,AGTBOUT=0D)ALTBOUT=0,AEQBOUT=0,AGTBOUT=12. As shown in Figure 1, what would the outputs of the 4-bit adder 74x283 be ( B ) when A3A2A1A0=0100,B3B2B1B0=1110 and S/A=1.A)C4=1, S3S2S1S0=0010D)C4=0, S3S2S1S0=1110B)C4=0, S3S2S1S0=0110C) C4=0, S3S2S1S0=1010Figure 13. Which of the following statements

8、is INCORRECT? ( A )A) A D latch is edge triggered and it will follow the input as long as the control input C is activelow.B) A D flip flop is edge triggered and its output will not change until the edge of the controllingCLK signal.C) An S-R latch may go into metastable state if both S and R are ch

9、anging from 11 to 00simultaneously.D)The pulse applying to any input of an S -R latch must meet the minimum pulse width requirement.4. The capacity of a memory that has 13 bits address bus and can store 8 bits at each address is ( B ).第 2 頁 共 7 頁學(xué)院姓名學(xué)號任課老師考場教室_選課號/座位號密封線以內(nèi)答題無效A)8192B) 65536C) 104amb

10、iguous ( C ).C) C and DD)256Which state in Figure 2 is5.NOTA) AB) BD) CWXX+YABZZ1DCFigure 2得 分III.in Figure 3,D Flip-Flop with asynchronous presetAnalyze the sequential-circuit as shownand clear inputs.151. Write out the excitation equations, transition equations and output equation.2. Assume the in

11、itial state Q Q =00, complete the timing diagram for Q ,Q and Z.5102121被 Q1異步清零Figure 3參考答案：激勵方程: D = Q ，D = Q1221轉(zhuǎn)移方程：Q * = D = Q ，Q * = D = Q【注意 Q1作用于異步清零端】112221輸出方程：Z = (CLK+Q )2第 3 頁 共 7 頁學(xué)院姓名學(xué)號任課老師考場教室_選課號/座位號密封線以內(nèi)答題無效得 分Analyze the sequential-circuit as shown below, which contains two 74x163

12、4-bit binary counter.151. Write out the logic expression LD_L for U and CLR_L for U .4122. Assume the initial state is 3 , write out the state sequence for the circuit.83103. Describe the modulusfor the circuit.InputsCurrent stateNext stateOutputsCLR_L LD_L ENT ENP QD QC QB QA QD* QC* QB* QA*RCOX011

13、1111XXX0111111X X X XX X X XX X X XX X X X0 0 0 00 0 0 10 0 1 00 0 1 1.1 1 1 100000000010 0 1 00 0 1 10 1 0 0.0 0 0 01 1111參考答案：1. LD_L = Q , CLR_L = (Q Q Q )35432. 狀態(tài)序列：十六進(jìn)制數(shù)表示：03H, 04H, 08H, 13H, 14H, 18H, 23H, 24H, 28H, 33H, 34H, 38H, 03H, 或十進(jìn)制數(shù)表示：3, 4, 8, 19, 20, 24, 35, 36, 40, 51, 52, 56, 3, 【

14、注意：計數(shù)值僅在時鐘觸發(fā)時刻變化】3. m = 24第 4 頁 共 7 頁學(xué)院姓名學(xué)號任課老師考場教室_選課號/座位號密封線以內(nèi)答題無效得 分Design a sequence signal generator with self-correcting to generate a serial output sequence of101100, using a 74x194 and a 74x151.1. List the transition table . 42. Write out the canonical sum of feedback function LIN.1543. Draw the circuit diagram.7The function table for 74x194stateFunctionQA* QB* QC* QD*【重要提示】ABCD序列發(fā)生器通常有如下幾種實(shí)現(xiàn)方法：一、觸發(fā)器+ 二、74x194 + 反饋邏輯。74x194 74x138、74x151、