低功耗前端設(shè)計(jì)課程

1、 蘇州中科集成電路設(shè)計(jì)中心 蘇州市中科職業(yè)培訓(xùn)學(xué)校 江蘇省集成電路人才培訓(xùn)基地蘇州工業(yè)園區(qū)金雞湖大道1355號(hào)國(guó)際科技園二期E301/401 HYPERLINK TelTel62889079 Mail:training 低功耗前端設(shè)計(jì)課程課程時(shí)長(zhǎng)： 2天（9:00-17:00）預(yù)計(jì)上課日期為6月29 日-30日（周五、周六）上課地點(diǎn)：蘇州工業(yè)園區(qū)金雞湖大道1355號(hào)國(guó)際科技園二期E401課程費(fèi)用： - 4500元/人（含聽(tīng)課、講義，午餐，茶歇等費(fèi)用），滿(mǎn)10人即開(kāi)班。- 2018年6月18日前報(bào)名并繳費(fèi)成功享9折優(yōu)惠 - 本課程有課后

2、測(cè)驗(yàn)，合格者將頒發(fā)結(jié)業(yè)證書(shū)授課對(duì)象：半導(dǎo)體產(chǎn)業(yè)相關(guān)在職人士或有相關(guān)技術(shù)或?qū)W生需求者，有數(shù)字集成電路方面工作2年經(jīng)驗(yàn)尤佳。3. 課程大綱：芯片功耗的組成。靜態(tài)功耗的組成，及其計(jì)算公式，及降低靜態(tài)功耗的方法概述。引出power gating的概念。動(dòng)態(tài)功耗的組成，及其各部分的計(jì)算公式，及降低動(dòng)態(tài)功耗的各種方法概述。提出toggle rate的概念，講述降低toggle rate的方法。引出DVFS的概念。動(dòng)態(tài)功耗與靜態(tài)功耗的沖突。Low power methodsClock gating門(mén)級(jí)功耗優(yōu)化Multi-VDD power designPower GatingDVFSMulti-Thresh

3、old logicMulti-Threshold cellMulti-VT cell的分類(lèi)及各自?xún)?yōu)缺點(diǎn)。使用multi-VT cell的方法及會(huì)給漏電帶來(lái)的好處。芯片時(shí)鐘架構(gòu)的低功耗設(shè)計(jì)考慮，如何做到auto clk gating等典型的時(shí)鐘結(jié)構(gòu)，講解clock divider，clock gate，OCC，clock mux的各種結(jié)構(gòu)及其優(yōu)缺點(diǎn)。重點(diǎn)講解目前芯片常用的clock組件的結(jié)構(gòu)。clock gating講解，clock structure中各層級(jí)clock gating的擺放方法及意義。動(dòng)態(tài)clock gating及靜態(tài)clock gating的區(qū)別及作用。POWER GATING

4、 Power gating overviewDynamic and leakage power介紹Power gating的對(duì)系統(tǒng)的影響power gating cell的類(lèi)型及優(yōu)缺點(diǎn)，目前芯片中常用power gating cell介紹。power gating cell的擺放方法介紹。芯片power gating domain的結(jié)構(gòu)介紹。isolation介紹為什么要isolationoutput or input Isolationinterface protocols and isolation State retention and restore methodsRetention

5、registersPower controller for retentionPartial vs full state retentionSystem level issues and retentionPower gating controlPower gating 控制時(shí)序介紹握手機(jī)制Recommendation and pitfalls for power gating controllersArchitectural issues for power gatingHierarchy and power gatingPower network and their control: (1

6、) external power rail switching (2) on-chip power gating.Power state table and AON logicMulti-voltage design為什么要multi-voltage designmulti-voltage 帶來(lái)的挑戰(zhàn)level-shift cell的介紹雙向level shift介紹高電壓到低電壓的轉(zhuǎn)變的level-shift低電壓到高電壓轉(zhuǎn)變的level-shift level shift 的自動(dòng)插入requency and voltage scaling designDynamic power and e

7、nergyVoltage scaling approachesDVFS (dynamic voltage and frequency scaling)AVS (adaptive voltage scaling)Level shift and isolationVoltage scaling interface - impact to timingControl of voltage scaling Memory低功耗設(shè)計(jì)Memory standbyMemory retentionMemory power downDual rail memory and single rail memoryIO

8、 /模擬模塊的低功耗設(shè)計(jì)考慮IO/analog IP retentionIO/analog IP power down總線的低功耗設(shè)計(jì)AXI c-channelDynamic clock switching and gating for busDDR 低功耗設(shè)計(jì)power down,light sleep; retention; DFSCPU 功耗設(shè)計(jì)考慮DVFS Standby and clock gatingPower down Wake up mechanism.系統(tǒng)級(jí)功耗設(shè)計(jì)考慮power domain partition - logical and physical hierarchy critical timing pathpower gating topologiesin-rush current managementdecoupling capacitor insertionsUPF introduction Power domain commands supply net, supply set and supply portISO insert commandsLS insert commandsPSW insert commands Power state table introduction MEM UPF, ANALO