模擬CMOS集成電路設(shè)計(jì)：3-Single-Stage Amplifiers

1、Chapter 3Single-Stage Amplifiers第2頁(yè)Analog DesignNon-linear systemTradeoffs3.2 Common-Source Stage3.2.1 Common-Source Stage with Resistive Load第3頁(yè)第4頁(yè)Common Source (cont.)How to maximize the voltage gain of a common-source stage?第5頁(yè)Common Source (cont.)第6頁(yè)Common Source (cont.)第7頁(yè)第8頁(yè)3.2.2 Common Source

2、 with Diode-Connected Load第9頁(yè)第10頁(yè)CS with Diode-Connected Load (cont.)第11頁(yè)Another method Large signal analysisGain is independent of bias current!第12頁(yè)Whats the final value of Vout if I1 drops to zero?I1 Vov2 For small I1,VGS2VTH2 Vout VDD-VTH2Output characteristic curve of Fig. 3.9CS with Diode-Conne

3、cted Load (cont.)第13頁(yè)This implies substantial voltage swing constraint.第14頁(yè)第15頁(yè)CS with Current Source Load第16頁(yè)Assuming ro2 large,3.2.4 CS with Triode Region Load第17頁(yè)CS with Source Degeneration第18頁(yè)CS with Source Degeneration (cont.)第19頁(yè)CS with Source Degeneration (cont.)第20頁(yè)第21頁(yè)第22頁(yè)CS Output Resistan

4、ce第23頁(yè)第24頁(yè)第25頁(yè)Lemma.第26頁(yè)Example 3.6 CS Gain Example第27頁(yè)3.3 Source Follower第28頁(yè)1. Large signal derivation第29頁(yè)第30頁(yè)Output Resistance第31頁(yè)第32頁(yè)第33頁(yè)Source Follower with Current Source Load第34頁(yè)第35頁(yè)3.4 Common Gate第36頁(yè)第37頁(yè)Common Gate (cont.)第38頁(yè)Common Gate (cont.)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)Output Resistance of CG第43頁(yè)第44頁(yè)3.5 Cascode Stage第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)How to increase gain?1. Cascode structure;2. For a given bias current, increase L of mosfet.第50頁(yè)Cascode Stage (cont.)第51頁(yè)第52頁(yè)第53頁(yè)The shielding property of cascodes diminishes if the cascode device enters the triode region.第54頁(yè)3.5.1 Folded Cascode第55頁(yè)第56頁(yè)第5