Quartus II 11.0功能仿真

1、Ln+出工Ln+壬uLn+壬u+_寸Ll_+_u?s至右mlll-LLBUEnjEcncud4illA匚DIJ-J-JCIdxLLI恕豈=|jILIILIUEiDEilldcudaj-LLI站IIIAELnt;illo-.Jd割口-ZJtiIDedIDAELn-JLJillojd匚llldg斶p啟苗tillledgillN期脅ol匚2呂述畫N廠一L_ld3匚IDELIBW5FtJluoCLIgmJ一PUJI“ffiHwftHelp區(qū)whatis什總nameofttiedeagnerttyforttnstxoject?Ths時(shí)臨iscast苗百喚andnujflexacttymatch(heen

2、btrnameInthedesanFile.Drrectory；Name；TopLevelEntitypage1ofSquartLE也軒E対stiig?？诤魌翠tfi些二_蟻仝IICaxelD:qijartU5WhatifthenameaFtheerojeizt?點(diǎn)擊NEXT,加入已經(jīng)存在的文件，有的話，瀏覽后在點(diǎn)擊all或者addall,如果沒有，直接點(diǎn)擊NEXT:AddFilespage2of5AndrCXVersionLIPHelpIXFiename:FileiWieTypeLibraryDesignEntry/SynthwTw!AddAllg.emov&Daw仃也口pertiasFin

3、ishCancel5eleCtthedesignfJesyou占nttoindude泊theproject.CkkAddAlltoodd曲IdisignffesinthftprojectdrettOiytothe甲QjeCt,rhlote:youcanaHaysadddiesgnfih字totheprojectlater.選擇器件，可以讓軟件自動(dòng)選擇，也可以自己指定，選擇區(qū)域如下：DevicefamilyPinctjurtdevictAvailabledevicas:UrnKW&RA忖toHarcKLcpide曲已resourcesfinishFho呵inAvaabled-iceslist0S

4、howadv-3needdt/kesAutodeMceselectedbytheFitter乜;SpcciFicdevkBselectedinAvaiabtedeviceslistHardCcpy：|C聊改CarlFamily&DeviceSettingspage3of5HardCopycnr-ipatrNeonlyPevfpes:AHFamiy:CyclnnaWGXNdrrbeCoreYyltdyeLEUcrI/O*HKBTrcwtsmitterClwnriielPMAGXDReceiverChannelPMAEP+CGX158F14C61.2VmOD01221EP4CGX15ef=i4C7

5、l.ZV1-14000221EP4CGXI5BF14CBL2Vmoo812a1,GX15BF1417n14301LB1nEP4CGXI5EAJ1K?価3440022EP4CGX15EWUCB1.2Vmoo二2和g15削山71.2140Z2E*J41,h_ir.亠1-.iiCompaniondevice選擇仿真軟件，這一步可以跳過，后面可以設(shè)置：*r*Finish罟EPG1WI7Designentry(fsynthesis:()()（*Device!SrTBLiaJtm!Tminganalysis:OdQOCCancel加入文件，點(diǎn)擊新建文件（紅線處），這里我們使用VerilogHDL：File

6、EditVievJProjectAssignments.FJ：oProfvigator占X輸入代碼并保存，模塊名要與保存的文件名稱相同，否則編譯報(bào)錯(cuò)：輸入完成后點(diǎn)擊編譯：編譯完成后顯示報(bào)告（這里我用的是另外一個(gè)工程的報(bào)告，所以RevisionName和Top-levelEntityName顯示為fifo3_128而不是quartus）：CowpilationReport-D:/FIFO3_128/fifo3_12-fifo3_128口回區(qū)ileEdkToafc邂indovtHelp筆M廣古TableofContentsFlowSummaryS-$iiAowSunwnarvF4ow咒tbngsF

7、lowNon-DeultGlobalSettingsFlbwEla|MedtimeFEqiajOSSurrmuryflowlogAnalysis&SynthesisFittaTrmtQuestTimingAnaiytfEDAhfetlistVAiterHSjmniaryJSimulationMessagesFlowStatusQuartus1VersionRevisionPtameTop-levelEntityNameFamilyDeviceTuningMcnjelsilotdllogitalehKntsTotalcombinationfunctionsDedicatedfogicregste

8、rsIritalrigiptar?Totalpins7italvirtiidlpins7atilm*rjrybitsEmbeddedMukiplier9-bitelementsTotalPLLsSuccess-FnMa251125:03201211.0Build15704/27/2011SJFullVersionffo3128Wo3J28CycloneIVEEP4CEll5F29f7EarlyFitterEstimation】65門比他Y%J124/114,480(1%)154/il%-80(1%)15454/529(10%)勺60a,鎌1磁(t%)0/532(0%)0/(0%)左下角顯示編譯

9、的項(xiàng)目，打鉤表示通過：胡DesignJi險(xiǎn)Hierarchy1Files-5inii輸入代碼完成后，要編寫測試平臺(Testbench)，輸入文件還是verilogHDL,只不過在保存的時(shí)候把后綴名改為vt：點(diǎn)擊Assignments-Settings-Simulation,toolname選ModelSim-Altera，F(xiàn)ormatforoutputnetlist選擇VerilogHDL，Timescale選擇1ns(可以根據(jù)自己需要調(diào)整)，點(diǎn)擊apply：點(diǎn)擊Processing-Start-StartTestBenchTemplateWriter:完成后，需要加入測試文件，如下圖所示：這里需要說明的是，TestbenchName和Toplevelmoduleintestbench要和之前寫的testbench模塊名相同，然后在Testbenchfiles里瀏覽文件并點(diǎn)擊Ad