數(shù)字邏輯設(shè)計(jì)及應(yīng)用教學(xué)課件：3-2CMOS電路的電氣特性

1、REVIEW OF LAST CLASS 1VDD = +5.0VVOUTVINTpTnVCCAZCMOS inverter常閉常開常閉常開inP 溝道N溝道2VCCAZVDD = +5.0VZABQ4Q1Q3CMOS 2-input NAND gateQ2CMOS inverter3 PMOS: when G is 0, Switch on; when G is 1, Switch off;NMOS: when G is 1, Switch on; when G is 0, Switch off;Two types of MOS transistor4CMOS inverter (INV)F

2、: get 1 from PMOS, get 0 from NMOS; When X=1, NMOS is on; When X=0, PMOS is on;5 NAND / NORNAND: NMOS serial , PMOS parallel; NOR: NMOS parallel, PMOS serial; 6 NAND / NORNAND: NMOS serial ; NOR: NMOS parallel;7 Output with positive logicBuffer AND8AND-OR-INVERT (COMS AOI )gate9 AOI / OAI103.4 Elect

3、rical Behavior of CMOS Circuits (CMOS電路的電氣特性)Logic voltage levels. ( 邏輯電壓電平)DC noise margins(直流噪聲容限)Fanout.(扇出)Speed, Power consumption(速度、功耗)Noise, Electrostatic discharge(噪聲、靜電放電)Open-drain outputs. Three-state outputs (漏極開路輸出、三態(tài)輸出)113.5.1 Logic Levels and Noise Margins 邏輯電平和噪聲容限VDD = +5.0VVOUTVIN

4、TpTn0 1 0112電壓傳輸特性VDD = +5.0VVOUTVINTpTn0 1 01電流傳輸特性iDvI12VDD13CMOS邏輯系列（HC）電平規(guī)格高態(tài)不正常狀態(tài)低態(tài)VOLmaxVILmaxVIHminVOHminVCC0.1V地0.1V0.7VCC0.3VCC典型值：VCC=5V+10%, Figure 3-26 Logic levels andnoise margins for the HC-series CMOS logic family. vcc014直流噪聲容限（DC noise margin）多大的噪聲會(huì)使最壞輸出電壓被破壞得不可被輸入端識(shí)別.高態(tài)不正常狀態(tài)低態(tài)VOLma

5、x=0.1VVILmax=1.35VVIHmin=3.15VVOHmin=4.4V30%VCC the LOW-state DC noise margin is 1.25 V =1.35-0.1(V)The HIGH state DC noise margin. Is 1.25 V=4.4-3.15(V) .1516VIK:輸入鉗位電壓在輸入端和輸出端加鉗位電路，使輸入和輸出不超過(guò)不超過(guò)規(guī)定電壓。 173.5.2 Circuit Behavior with Resistive Loads (帶電阻性負(fù)載的電路特性)(P103)183.5.2 Circuit Behavior with Resi

6、stive Loads(帶電阻性負(fù)載的電路特性)(P103)要求有一定的驅(qū)動(dòng)電流才能工作VCCAZVCCRThevRpRnVThev +VOUTVINaThvenin equivalent network19REMEMBERING THVENIN Any two-terminal circuit consisting of only voltage sources and resistors can be modeled by a Thvenin equivalent consisting of a single voltage source in series with a single r

7、esistor. The Thvenin voltage is the open-circuit voltage of the original circuit, and the Thvenin resistance is the Thvenin voltage divided by the short-circuit current of the original circuit.20Example 1 (P104)21Resistive model for CMOS LOW outputwith resistive load.22Resistive model for CMOS HIGH

8、outputwith resistive load.23VOLmaxIOLmax輸出為低態(tài)時(shí) VOUT 1MRn電阻性負(fù)載100 Sinking current吸收電流24VOHminIOHmax輸出為高態(tài)時(shí) VOUT = VOHmin輸出端提供電流 sourcing current能提供的最大電流 IOHmax （拉電流）VCC = + 5.0VRpRn1M電阻性負(fù)載200 Sourcing current 提供電流25VOUT = 0VCC = + 5.0VRThevVThev +VIN = 1VCC = + 5.0VRThevVThev +VOUT = 1VIN = 0輸出為低態(tài)時(shí)，估計(jì)

9、吸收電流：輸出為高態(tài)時(shí)，估計(jì)提供電流：26EXAMPLE 2 (P107)273.5.3 Circuit Behavior with Nonideal Inputs (P108)283.5.3 Circuit Behavior with Nonideal Inputs非理想輸入時(shí)的電路特性VCC = + 5.0V4002.5kVIN 1.5VVOUT 4.31VVCC = + 5.0V4k200VIN 3.5VVOUT 0.24V輸出電壓變壞（有電阻性負(fù)載時(shí)更差）更糟糕的是：Iwasted ， Pwasted 29Example 3 (P110)303.5.4 Fanout(P111)313.

10、5.4 Fanout （扇出）The fanout of a logic gate is the number of inputs that the gate can drive without exceeding its worst-case loading specifications. The fanout depends not only on the characteristics of the output, but also on the inputs that it is driving. Fanout must be examined for both possible ou

11、tput states, HIGH and LOW. 在不超出其最壞情況負(fù)載規(guī)格的條件下， 一個(gè)邏輯門能驅(qū)動(dòng)的輸入端個(gè)數(shù)。扇出需考慮輸出高電平和低電平兩種狀態(tài) 總扇出min（高態(tài)扇出，低態(tài)扇出）直流扇出 和 交流扇出32EXAMPLE 3 (P111) IImax for an HC-series CMOS input in any state is 1 A .The LOW-state fanout for an HC-series output driving HC-series inputs is 20. IImax for an HC-series CMOS input in any

12、state is 1 A .The HIGH-state fanout for an HC-series output driving HC-series inputs is 20.33EXAMPLE 4CMOS(TTLoutput level)CMOSCMOS the fanout of an HC-series output driving HC-series inputs at TTLlevels is 4000.直流扇出343.5.5 Effects of Loading(負(fù)載效應(yīng)) 輸出負(fù)載大于它的扇出能力時(shí)（P111） In the LOW state, the output vo

13、ltage (VOL) may increase beyond VOLmax.In the HIGH state, the output voltage (VOH) may fall below VOHmin.輸出電壓變差Propagation delay to the output may increase beyond specifications. Output rise and fall times may increase beyond their specifications.傳輸延遲和轉(zhuǎn)換時(shí)間變長(zhǎng) The operating temperature of the device m

14、ay increase, thereby reducing the reliability of the device and eventually causing device failure. 溫度可能升高，可靠性降低，器件失效.353.5.6 Unused Inputs(不用的CMOS輸入端)不用的CMOS輸入端絕對(duì)不能懸空XZ1k+5VXZ增加了驅(qū)動(dòng)信號(hào)的電容負(fù)載，使操作變慢XZ1k363.6 CMOS Dynamic Electrical Behavior(P114)373.6 CMOS Dynamic Electrical Behavior CMOS動(dòng)態(tài)電氣特性考慮兩個(gè)方面：速度功

15、耗轉(zhuǎn)換時(shí)間（transition time）傳播延遲（propagation delay）靜態(tài)功耗（static power dissipation）動(dòng)態(tài)功耗（dynamic power dissipation）383.6 CMOS Dynamic Electrical Behavior (CMOS動(dòng)態(tài)電氣特性) CMOS器件的速度和功耗在很大程度上取決于器件及其負(fù)載的動(dòng)態(tài)特性。速度取決于兩個(gè)特性：transition time（轉(zhuǎn)換時(shí)間）propagation delay（傳播延遲）邏輯電路的輸出從一種狀態(tài)變?yōu)榱硪环N狀態(tài)所需的時(shí)間從輸入信號(hào)變化到產(chǎn)生輸出信號(hào)變化所需的時(shí)間393.6.1 Tr

16、ansition Time (轉(zhuǎn)換時(shí)間) rise time(上升時(shí)間) tr fall time(下降時(shí)間) tf the “on” transistor resistance(晶體管的“導(dǎo)通”電阻)stray capacitance(寄生電容)VCC = + 5.0VRLRpRnVL+CL電容兩端電壓不能突變?cè)趯?shí)際電路中可用時(shí)間常數(shù)近似轉(zhuǎn)換時(shí)間P115 Figure 3-3640Example 4 (P117)estimates of 10 ns for fall time .41EXAMPLE 5 (P117)estimates of 20 ns for rise time .423.6.2 Propagation Delay(傳播延遲)P83 圖3-42VINVOUT信號(hào)通路：一個(gè)特定輸入信號(hào)到邏輯元件的 特定輸出信號(hào)所經(jīng)歷的電氣通路。433.6.2 Propagation Delay(傳播延遲)信號(hào)通路：一個(gè)特定輸入信號(hào)到邏輯元件的 特定輸出信號(hào)所經(jīng)歷的電氣通路。443.6.3 Power Consumption(功率損耗)static power dissi