數(shù)字電路英文版第五單元PPT學習教案

1、數(shù)字電路英文版第五單元數(shù)字電路英文版第五單元CHAPTER 5 Dual symbol ( 對偶符號 ) Node ( 節(jié)點 ) Signal tracing (信號跟蹤) Universal gate ( 萬能門 ) Combinational logic (組合邏輯)Sequential logic ( 時序邏輯) 第1頁/共74頁or more gate inputs.第2頁/共74頁第3頁/共74頁第4頁/共74頁In Chapter 4, you learned that SOP expressions are implemented with an AND gate for eac

2、h product term and one OR gate for summing all of the product terms. This SOP implementation is called ANDOR logic and is the basic form for realizing standard Boolean functions.2.第5頁/共74頁In this section, the ANDOR and the AND-OR-Invert are examined; and the exclusive-OR and exclusive-NOR gates, whi

3、ch are actually a form of AND-OR logic, are covered.3.第6頁/共74頁AND-OR Logic ( SOP ) ABDCABXCD&1ABCDXX = AB + CD4.Fig.5-1第7頁/共74頁 Input Output A B C D AB CD X 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0

4、 1 0 1 0 0 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1TABLE 5-1Truth table for the AND-OR logic in Fig.5-15.X = AB + CD第8頁/共74頁AND-OR-Invert Logic ( POS )ABDCABXCD&1ABCDXX = AB + CD = (A + B)(C + D) 6.第9頁/共74頁ABXExclusive-OR LogicABXX = AB+AB = A BABX=17.ABAB第10頁/共7

5、4頁 Input OutputA B X 0 0 0 0 1 1 1 0 1 1 1 08.X = AB+AB = A B第11頁/共74頁ABXExclusive-NOR LogicXORABXX=AB+ABX=AB+ABABAB9.第12頁/共74頁ABXX=1X = AB+AB =AB+AB = A B10.第13頁/共74頁In this section, examples are used to illustrate how to implement a logic circuit from a Boolean expression or a truth table. Minimiz

6、ation of a logic circuit using the methods covered in Chapter 4 is also discussed.11.第14頁/共74頁From a Boolean Expression to a Logic CircuitLets examine the following Boolean expression :X=AB + CDEANDORX=AB+CDEABCDE12.第15頁/共74頁As another example, lets implement the following expression :X=AB (CD + EF)

7、ANDNOTORANDABCDEFCDEFDCD+EFX=AB (CD + EF)13.(a)第16頁/共74頁X=AB (CD + EF)= ABCD + ABEFABCDABEFDABCEF X=ABCD + ABEF( Sum-of-products implementation of circuit in part (a). )14.第17頁/共74頁From a Truth Table to a Logic Circuit Input OutputA B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1

8、 0ABCABCX = ABC + ABC15.第18頁/共74頁X = ABC + ABCXABCABCAABBCC16.第19頁/共74頁Up to this point, combinational circuits implemented with AND gates, OR gates, and inverters have been studied. In this section, the universal property of the NAND gate and the NOR gate is discussed. 17.第20頁/共74頁The universality

9、of the NAND gate means that it can be used as an inverter and that combinations of NAND gates can be used to implement the AND, OR, and NOR operations. Similarly, the NOR gate can be used to implement the inverter, AND, OR, and NAND operation.18.第21頁/共74頁The NAND Gate as a Universal Logic ElementBBA

10、AAAAABAB=ABABA(a) A NAND gate used as an inverter(b) Two NAND gate used as an AND gate19.第22頁/共74頁A B=A+BAABBABA+B(c) Three NAND gate used as an OR gateAABBABA+BA+BAB=A+B(d) Four NAND gate used as an NOR gateG1G2G3G1G2G3G420.第23頁/共74頁The NOR Gate as a Universal Logic ElementBBAAAAAA+BA+BA+BA(a) A NO

11、R gate used as an inverter(b) Two NOR gate used as an OR gate21.第24頁/共74頁A+ B=ABAABBAB(c) Three NOR gate used as an AND gateABABA BAB(d) Four NOR gate used as an NAND gateABA BABG1G2G3G1G2G3G422.第25頁/共74頁In this section, you will see how NAND and NOR gates can be used to implement a logic function.

12、Recall from Chapter 3 that the NAND gate also exhibits an equivalent operation called the negative-OR and that the NOR gate exhibits an equivalent operation called the negative-AND. 23.第26頁/共74頁You will see how the use of the appropriate symbols to represent the equivalent operations makes “reading”

13、 a logic diagram easier.24.第27頁/共74頁NAND LogicAB = A + BX= (A B)( C D) = (A + B)(C + D) = (A + B)+(C + D) = A B + C D = A B + C DBAABCDCDX=AB+CDNANDnegative-OR25.第28頁/共74頁BACDX=AB+CDG2 acts as ANDG1 acts as ORG3 acts as ANDBACDBACDAB+CDAB+CDBubbles cancelBubbles cancel26.第29頁/共74頁NAND Logic Diagrams

14、AABBCCDDEFEF(AB+C)D+EFXX=ABCD EF =ABCD+EF =(AB+C)D+EF =(AB+C)D+EFABAB+C(AB+C)DEFABABCABCDEFBubbles cancels barBubbles adds bar to CBubbles cancels barORANDORAND27.第30頁/共74頁NOR LogicA + B = A BX = A+ B + C + D = (A + B)(C + D) = (A + B)(C + D)C+DNORnegative-ANDCDAB28.A+B第31頁/共74頁BACDX=(A+B)(C+D)G2 ac

15、ts as ORG1 acts as ANDG3 acts as ORBACDX=(A+B)(C+D)Bubbles cancelBubbles cancel29.A + B = A B第32頁/共74頁NOR Logic DiagramsAABBCCDDEFEF(A+B)C+D(E+F)X=A+B+C+D+ E+F =(A+B+C+D)(E+F) =(A+B)C+D)(E+F) =(A+B)C+D)(E+F)A+B(A+B)C(A+B)C+DE+FA+BA+B+CA+B+C+DE+FBubbles cancels barBubbles adds bar to CBubbles cancels

16、 barANDORANDOR30.第33頁/共74頁Several examples of general combinational logical circuits with pulse waveform inputs are examined in this section. Keep in mind that the logical operation of each gate is the same for pulse inputs as for constantlevel inputs.31.第34頁/共74頁The output of a logic circuit at any

17、 given time depends on the inputs at that particular time, so the relationship of the time-varying inputs is of primary importance.32.第35頁/共74頁1. The output of an AND gate is HIGH only when are HIGH at the same time.2. The output of an OR gate is HIGH only when of its inputs is HIGH.3. The output of

18、 a NAND gate is LOW only when are HIGH at the same time.4. The output of an NOR gate is LOW only when of its inputs is HIGH.33.第36頁/共74頁EXAMPLE 511. Showing the outputs of G1, G2, and G3 with input waveforms, A and B, as indicated.ABG1G2G3X=AB + AB34.第37頁/共74頁FIGURE 5-33ABXG2 output=ABG3 output= AB3

19、5.X=AB + AB第38頁/共74頁EXAMPLE 512. Determine the outputs waveforms X for the logic circuit as follow:ABCDX=Y3+Y4=Y1C+Y2D=(A+B)C+CD=AC+BC+CDY1=A+BY3=Y1CY2=CY4=Y2D36.第39頁/共74頁BACDX37.Y1=A+BY2=CY3=Y1CY4=Y2D=AC+BC+CDACACCDBC第40頁/共74頁Using K-maps to Eliminate Timing HazardsAL = A AAAAL第41頁/共74頁AALBCCACBCCB

20、ACBCLL = AC + BC第42頁/共74頁 ABC000111100 1 1 1 1 1L = AC + BC + AB ( 111 110 )ACBACBCLAB第43頁/共74頁00000AB0000010111111010CD0000( A + C )( B + C )( A + C + D )( A + B + D )ACBCACDACBCACDABDLL第44頁/共74頁Chapter 5: Combinational LogicTrue/False1. The NAND gate is an example of combinational logic.2. Fig. 5-

21、1 is an example of the implementation of AND-OR-INVERTER logic.ABCDX38.第45頁/共74頁3. The abbreviation for an exclusive-OR gate is XOR.4. X= ABC+BCD is in the form of a sum-of products expression.5. The K-map in Fig. 5-2 shows the correct implementation of the expression, X=ACD+ AB(CD+BC).A BA BA BA BC

22、 DC DC DC D000000000000111139.第46頁/共74頁6. NAND gates cannot be used to construct NOR gates.7. NOR gates can be used to construct AND gates.8. The expressions, AB and A + B, are equivalent.9. The effect of an inverted output being connected to the inverting input of another gate is to effectively eli

23、minate one of the inversions, resulting in a single inversion.40.第47頁/共74頁10. The logic circuit and associated waveforms shown in Fig. 5-3 are correct.ABCXABCX41.第48頁/共74頁Multiple Choice11. Which figure in Fig. 5-4 represents AND-OR logic?BACDXABCXACXABCXBa.b.c.d.&142.第49頁/共74頁12. Which of the f

24、igures in Fig. 5-5(a-d) is equivalent to Fig. 5-5(e)?ABCDABCDABCDABCDABCDXXXXXa.b.c.d.e.43.第50頁/共74頁13. Which of the figures in Fig. 5-6(a-d) is equivalent to Fig. 5-5(e)?ABABABXXXa.b.d.e.Xc.44.第51頁/共74頁14. Which of the following logic expressions represents the logic diagram in Fig. 5-7?a.X=AB+AB b

25、. X=AB+ABc. X=AB +AB d. X=AB +ABABX45.第52頁/共74頁15. What type of logic circuit is represented by Fig. 5-7?a. XOR b. XNOR c. XAND d. XNAND46.第53頁/共74頁16. The logic expressions for in Fig. 5-8 is ?a. X=ABC+ACD b. X=(AB)(ACCD)c. X=(AB) (AC+CD) d. X=ABC(CBD)ABCDX47.第54頁/共74頁17. The expended expressions f

26、or in Fig. 5-8 is ?a. X=A(BC+CD )b. X=ACD+ABCD +ABCc. X=ABC+BCDd. X=AABCD +AABCD +ABCD48.第55頁/共74頁18. Use Boolean algebra to determine the simplest output equation for Fig. 5-8 .(note:The instructor may require you to show your work for this problem.)a. X=ABCDb. X=A(BC+CD)c. X=ABC+BCDd. X=A(BCD)49.第

27、56頁/共74頁19. Use K-map to determine the simplest output equation for Fig. 5-8 .(note:The instructor may require you to show your work for this problem.)a. X=ABCDb. X=A(BC+CD)c. X=ABC+BCDd. X=A(BCD)50.第57頁/共74頁20. Which circuit in Fig. 5-9 implements the equation, X=AB+AC+ABC?ABCABCABCABCABCABCBCAXXXX

28、a.b.c.d.51.第58頁/共74頁22. How many gates, including inverters, are required to implement the equation, X=ACD+AB(CD+BC), before simplification?a.5 b. 9 c. 7 d. 323. How many gates, including inverters, are required to implement the equation, X=ACD+AB(CD+BC), after simplification with algebra?a.5 b. 9 c

29、. 7 d. 353.第59頁/共74頁24. How many gates, including inverters, are required to implement the equation, X=ACD+AB(CD+BC), after simplification with a K-map?a.5 b. 9 c. 7 d. 354.第60頁/共74頁25. The NAND gate is referred to as a “universal” gate, because it .a.Can be found in almost all digital circuits.b. C

30、an be used to build all the other types of gates.c.Is used in all the countries of the world. d. Was the first gate to be integrated.55.第61頁/共74頁26. Which of the figures in Fig. 5-11(a-d) represents the NAND implementation of a NOR gate?a.c.b.d.56.第62頁/共74頁27. Which of the figures in Fig. 5-11(a-d)

31、represents the NAND implementation of an OR gate?28. Which of the figures in Fig. 5-11(a-d) represents the NAND implementation of an INVERTER gate?57.第63頁/共74頁29. The relationship between a NAND gate and a negative-OR gate is expressed by = .a.AB=A+B b. A+B=A+Bc. AB= A+B d. AB= A +B58.第64頁/共74頁30. W

32、hich of the figures in Fig. 5-12(a-d) is the logical equivalent of Fig. 5-12(e)?a.b.c.d.e.59.第65頁/共74頁31. When the inverted output of the gate is connected to the inverted input of another gate, .a.the inversions cancel.b. a double inversion occurs and the signal is inverted.c.one inversion cancels

33、the other and only a single inversion results.d. All of the above are correct.60.第66頁/共74頁32. Why are multiple NAND gates used to replace other single function gates?a.It is easier to design logic circuits with a single gate type, since you only have to fully understand how one type of gate works.b.NAND gates are cheaper than any other type of gate.c.NAND gates are packaged more densely on ICs than other types of gates.d.It makes it possible to use spare portions of