C28x的儲存空間及外部接口

1、4 4 4.1 4.1 存儲空間的映射存儲空間的映射圖圖4.3 4.3 外部存儲器接口（外部存儲器接口（XINTFXINTF）4.14.1 TSM320F2812TSM320F2812的存儲器映射圖的存儲器映射圖4.14.1 TSM320F2812TSM320F2812的存儲器映射圖（續(xù)）的存儲器映射圖（續(xù)）4.1.14.1.1 PF04.1.24.1.2 PF14.1.34.1.3 PF24.24.2 （1 1） 特點特點（2 2）電源模式）電源模式（4 4）流水線模式）流水線模式（5 5） 相關(guān)寄存器相關(guān)寄存器（3 3）Flash/OTPFlash/OTP的訪問的訪問4.2.14.2.1

2、(1) (1) 多扇區(qū)多扇區(qū)(2) (2) 代碼安全性代碼安全性(3) (3) 低功耗模式低功耗模式(4) (4) 基于基于CPUCPU頻率可進行調(diào)整的配置等待周期頻率可進行調(diào)整的配置等待周期(5) (5) 可改善性能的可改善性能的FlashFlash流水線模式流水線模式(1)(1) 4.2.24.2.2 v CPUCPU的訪問將自動初始化的訪問將自動初始化Flash/OTPFlash/OTP的電源模式，使其轉(zhuǎn)換到工作的電源模式，使其轉(zhuǎn)換到工作狀態(tài)或讀狀態(tài)。狀態(tài)或讀狀態(tài)。 u這是這是DSCDSC復(fù)位后的狀態(tài)復(fù)位后的狀態(tài)u存儲體及其驅(qū)動（激勵）電路處于休眠狀態(tài)（功耗最低）。存儲體及其驅(qū)動（激勵）

3、電路處于休眠狀態(tài)（功耗最低）。u CPUCPU的讀操作或?qū)Φ淖x操作或?qū)lash/OTPFlash/OTP存儲器的取指訪問都將暫停存儲器的取指訪問都將暫停CPUCPU。v CPUCPU的訪問將自動初始化的訪問將自動初始化Flash/OTPFlash/OTP的電源模式，使其轉(zhuǎn)換到工作狀的電源模式，使其轉(zhuǎn)換到工作狀態(tài)或讀狀態(tài)。態(tài)或讀狀態(tài)。 u存儲體及其驅(qū)動（激勵）電路處于待機狀態(tài)。存儲體及其驅(qū)動（激勵）電路處于待機狀態(tài)。u CPUCPU的讀操作或?qū)Φ淖x操作或?qū)lash/OTPFlash/OTP存儲器的取指訪問都將暫停存儲器的取指訪問都將暫停CPUCPU。v FlashFlash流水線的預(yù)取機制可

4、以改善取指性能流水線的預(yù)取機制可以改善取指性能 。 u存儲體及其驅(qū)動（激勵）電路處于工作狀態(tài)（功耗最大）。存儲體及其驅(qū)動（激勵）電路處于工作狀態(tài)（功耗最大）。u CPUCPU的讀操作或?qū)Φ淖x操作或?qū)lashFlash或或OTPOTP存儲器映像區(qū)的取指訪問的等待狀態(tài)均由存儲器映像區(qū)的取指訪問的等待狀態(tài)均由FBANKWAITFBANKWAIT或或FOTPWAITFOTPWAIT寄存器控制寄存器控制 。u 讀操作或從讀操作或從Flash/OTPFlash/OTP中執(zhí)行指令，中執(zhí)行指令，F(xiàn)lash/OTPFlash/OTP存儲體存儲體及其驅(qū)動（激勵）電及其驅(qū)動（激勵）電路路處于相同的電源模式處于相同

5、的電源模式 。u 改變電源寄存器的改變電源寄存器的PWRPWR模式位模式位v 同時把同時把Flash/OTPFlash/OTP存儲體變?yōu)榈凸臓顟B(tài)存儲體變?yōu)榈凸臓顟B(tài)v 需要通過執(zhí)行需要通過執(zhí)行Flash/OTPFlash/OTP存儲器之外的代碼才能訪問該寄存器。存儲器之外的代碼才能訪問該寄存器。(1) 32(1) 32位取指位取指(2) 16(2) 16位或位或3232位數(shù)據(jù)空間讀位數(shù)據(jù)空間讀(3) 16(3) 16位程序空間讀位程序空間讀(1) Flash(1) Flash的隨機訪問的隨機訪問(2) Flash(2) Flash的頁訪問的頁訪問(3) OTP(3) OTP的訪問的訪問配置寄

6、存器配置寄存器等待等待8 8個周期個周期轉(zhuǎn)移到或調(diào)用轉(zhuǎn)移到或調(diào)用配置代碼配置代碼返回返回繼續(xù)執(zhí)行繼續(xù)執(zhí)行XINTF, SARAM,Flash, OTP, ROMXINTF, SARAMXINTF, SARAM,Flash, OTP, ROM由于CPU流水線造成的8個等待FSTATUSFSTATUSVDD3V Status Latch BitWhen set, this bit indicates that the 3 VSTAT signal from the pump module went to a high level. This signal indicates that the 3

7、V supply went out of allowable range. This bit is cleared by writing a 1, writes of 0 are ignored.FSTATUSFSTATUSBank and Pump Standby To Active Wait Counter Status BitIf the bit is set, then the counter is counting; If the bit is 0, then the counter is not counting.Bank and Pump Sleep To Standby Wai

8、t Counter Status BitPower Modes Status BitsFSTDBYWAITFSTDBYWAIT1Bank and Pump Sleep To Standby Wait CountBank and Pump Sleep To Standby Wait CountThe power mode for the bank and pump are set for standby mode. The counter then counts down to zero before the PWRS bits are set to standby mode. If a CPU

9、 read or fetch access to the Flash bank/OTP initiated the process, the CPU is stalled until the access completes.The STDBYWAIT bits specify the number of CPU clock cycles (0.511 SYSCLKOUT cycles) of delay. This register should be left in its default stateFACTIVEWAITFACTIVEWAITFBANKWAITFBANKWAIT1PAGE

10、WAIT PAGEWAIT Flash Paged Read Wait StatesFlash Paged Read Wait StatesThese register bits specify the number of wait states for a paged read operation in CPU clock cycles (0.15 SYSCLKOUT cycles) to the banks.1PAGEWAIT PAGEWAIT Flash Random Read Wait StatesFlash Random Read Wait StatesYou must set RA

11、NDWAIT to a value greater than or equal to the PAGEWAIT setting. No hardware is provided to detect a PAGEWAIT value that is greater then RANDWAIT.When enabling Flash pipeline mode, you must set PAGEWAIT and RANDWAIT to a value greater than zero.FOTPWAITFOTPWAIT1OTPWAIT OTPWAIT OTP Read Wait StatesOT

12、P Read Wait StatesThese register bits specify the number of wait states for a read operation in CPU clock cycles (0.31 SYSCLKOUT cycles) to the OTP. OTPWAIT must be set greater than 0. The device-specific data sheet for the minimum time required for an OTP or ROM access.4.3 4.3 外部外部存儲器接口（存儲器接口（XINTF

13、）（1 1） 外部存儲器接口信號外部存儲器接口信號（5 5）XINTFXINTF的時序圖的時序圖（2 2）XINTF XINTF 的配置的配置（3 3）XINTF XINTF 的配置寄存器的配置寄存器（4 4）XINTF XINTF 的配置小結(jié)的配置小結(jié)（6 6）XINTFXINTF的設(shè)計示例的設(shè)計示例u 在改變在改變XINTFXINTF的配置和時序的過程中，不允許對的配置和時序的過程中，不允許對XINTFXINTF進行存??；進行存??；u 堆棧也不能位于外部存儲區(qū)。堆棧也不能位于外部存儲區(qū)。uXINTF XINTF 的時序約束的時序約束X2TIMINGLEADDECN= XRDLEAD2,XR

14、DLEAD=13uXRDLEADXRDLEADp如果如果 XRDLEAD0XRDLEAD0p如果如果 XRDLEADXRDLEAD0 0， 無效無效X2TIMINGACTIVEDECN= XRDACTIVE2,XRDACTIVE=07uXRDACTIVEXRDACTIVEX2TIMINGTRAILDECN= XRDTRAIL2,XRDTRAIL=03uXRDTRAILXRDTRAILX2TIMINGLEADDECN= XWRLEAD2,XWRLEAD=13uXWRLEADXWRLEADp如果如果 XWRLEAD0XWRLEAD0p如果如果 XWRLEADXWRLEAD0 0， 無效無效X2TI

15、MINGACTIVEDECN= XWRACTIVE2,XWRACTIVE=07uXWRACTIVEXWRACTIVEX2TIMINGTRAILDECN= XWRTRAIL2,XWRTRAIL=03uXRDTRAILXRDTRAILTableTable.XTIMCLK XTIMCLK 和和 XCLKOUTXCLKOUT的關(guān)系圖的關(guān)系圖.一般的讀時序圖一般的讀時序圖.一般的寫時序圖一般的寫時序圖.XTIMCLK XTIMCLK 和和 XCLKOUTXCLKOUT的關(guān)系圖的關(guān)系圖.一般的讀時序圖一般的讀時序圖.一般的寫時序圖一般的寫時序圖Taking the CY7C1061AV33 for exa

16、mpleu 16-Mbit (1M x 16) Static RAM16-Mbit (1M x 16) Static RAMu High speed: tHigh speed: tAAAA = 10 ns = 10 nsu Low active power: 990 mW (max)Low active power: 990 mW (max)u Operating voltages of 3.3 Operating voltages of 3.3 0.3V 0.3Vu 2.0V data retention2.0V data retentionu Automatic power down wh

17、en deselectedAutomatic power down when deselectedu TTL compatible inputs and outputsTTL compatible inputs and outputsu Easy memory expansion with CE1 and CE2 Easy memory expansion with CE1 and CE2 featuresfeaturesu package :54-pin TSOP II and FBGApackage :54-pin TSOP II and FBGARead Waveform No.1 Read Waveform No.1 Read Waveform No