集成電路分析與設(shè)計(jì)

1、CMOSCMOS數(shù)字集成電路數(shù)字集成電路(CMOS digital IC)(CMOS digital IC)IC的發(fā)展歷史及現(xiàn)狀(History of IC)IC 設(shè)計(jì)流程和方法(Design process and Methodology)IC 制造工藝技術(shù)(Fabrication process)IC EDA（CAD）工具使用(EDA tools)CMOSCMOS反相器設(shè)計(jì)反相器設(shè)計(jì)(CMOS Inverter)(CMOS Inverter)CMOSCMOS組合邏輯門設(shè)計(jì)組合邏輯門設(shè)計(jì)(Combinational Logic Circuit)(Combinational Logic Cir

2、cuit)CMOSCMOS時(shí)序邏輯電路設(shè)計(jì)時(shí)序邏輯電路設(shè)計(jì)(Sequential Logic Circuit )(Sequential Logic Circuit )IC 版圖設(shè)計(jì)(Layout)IC 仿真技術(shù)(Simulation)存儲(chǔ)器電路設(shè)計(jì)介紹(Memory Circuits)模擬IC設(shè)計(jì)介紹(Analog IC)課程性質(zhì)：是一門專業(yè)基礎(chǔ)課程課程性質(zhì)：是一門專業(yè)基礎(chǔ)課程主要介紹主要介紹CMOSCMOS數(shù)字集成電路設(shè)計(jì)的基礎(chǔ)知識(shí)數(shù)字集成電路設(shè)計(jì)的基礎(chǔ)知識(shí)共共4040課時(shí)（課時(shí)（3232理論課時(shí)理論課時(shí)+8+8實(shí)驗(yàn)課時(shí)）實(shí)驗(yàn)課時(shí)）完成完成4 4個(gè)實(shí)驗(yàn)個(gè)實(shí)驗(yàn)對(duì)準(zhǔn)備從事對(duì)準(zhǔn)備從事ICIC行業(yè)的

3、學(xué)生來講，本課程只是一行業(yè)的學(xué)生來講，本課程只是一個(gè)基礎(chǔ)，還需要繼續(xù)深入學(xué)習(xí)更多關(guān)于個(gè)基礎(chǔ)，還需要繼續(xù)深入學(xué)習(xí)更多關(guān)于ICIC設(shè)計(jì)設(shè)計(jì)的知識(shí)，如數(shù)字的知識(shí)，如數(shù)字ICIC深入，模擬深入，模擬ICIC，RF ICRF IC等。等。實(shí)驗(yàn)一（實(shí)驗(yàn)一（2 2學(xué)時(shí)）學(xué)時(shí)）反相器電路設(shè)計(jì)（ Simulation and Layout ）實(shí)驗(yàn)二（實(shí)驗(yàn)二（2 2學(xué)時(shí)）學(xué)時(shí)）NAND電路設(shè)計(jì)（ Simulation and Layout ）實(shí)驗(yàn)三（實(shí)驗(yàn)三（2 2學(xué)時(shí)）學(xué)時(shí)）AND 電路設(shè)計(jì)（ Simulation and Layout ）實(shí)驗(yàn)四（實(shí)驗(yàn)四（2 2學(xué)時(shí)）學(xué)時(shí)）D觸發(fā)器電路設(shè)計(jì)（ Simulation

4、 and Layout ）完成一個(gè)完成一個(gè)4 4 4 SRAM 4 SRAM芯片的設(shè)計(jì)芯片的設(shè)計(jì)3 3人一組人一組項(xiàng)目過程項(xiàng)目過程：A A 期中期中Oral Oral presentationpresentationB B 期末期末Oral Oral presentationpresentationC C 項(xiàng)目報(bào)告書一份項(xiàng)目報(bào)告書一份D 3D 3人項(xiàng)目成績(jī)相同人項(xiàng)目成績(jī)相同課堂提問和作業(yè)課堂提問和作業(yè) 10%10%實(shí)驗(yàn)實(shí)驗(yàn) 20%20%考試考試 （開卷）（開卷） 70%70%規(guī)則：規(guī)則：（1 1）1 1個(gè)問題和個(gè)問題和4 4次作業(yè)，每次次作業(yè)，每次/ /個(gè)個(gè)2 2分，共分，共1010分；分；（

5、2 2）每個(gè)實(shí)驗(yàn)完成得）每個(gè)實(shí)驗(yàn)完成得5 5分，共分，共2020分；分； （3 3）點(diǎn)名）點(diǎn)名1 1次不到，次不到，1010分沒了；分沒了； （4 4）抄作業(yè)，抄實(shí)驗(yàn)報(bào)告，相應(yīng)分?jǐn)?shù)沒了；）抄作業(yè)，抄實(shí)驗(yàn)報(bào)告，相應(yīng)分?jǐn)?shù)沒了；（5 5）請(qǐng)假規(guī)則：必須有正規(guī)請(qǐng)假手續(xù)和課前請(qǐng)假。）請(qǐng)假規(guī)則：必須有正規(guī)請(qǐng)假手續(xù)和課前請(qǐng)假。教材中文版 周潤(rùn)德等 譯，數(shù)字集成電路設(shè)計(jì)透視第二版，電子工業(yè)出版社 (Jan M. Rabaey, et al. Digital Integrated Circuits, 2nd e, Prentice Hall, 2004)參考書Sung-Mo (Steve) Kang, Yusu

6、f Leblebici, CMOS Digital Integrated Circuits Analysis & Design, 3rd Edition, Mc Graw-Hill 2003R. Jacob Baker, CMOS Circuit Design, Layout, and simulation, 3rd Edition, Wiley, 2010韓雁，集成電路設(shè)計(jì)CAD/EDA工具實(shí)用教程，機(jī)械工業(yè)出版社，2010模擬集成電路Razavi，模擬CMOS集成電路設(shè)計(jì)，清華大學(xué)出版社，2005通用參考書（Bible）威斯特，CMOS超大規(guī)模集成電路設(shè)計(jì)，第三版，中國(guó)電力出版社C

7、MOS (complementary metal oxide semiconductor)IC (integrated circuit)VLSI (very large scale integrated)ULSI (ultra-large scale integrated)MOSFET (metal oxide semiconductor field effect transistors)SPICE (simulation program with integrated circuit emphasis)為什么需要集成電路？與以前的集成電路設(shè)計(jì)相比，為什么現(xiàn)在的集成電路設(shè)計(jì)出現(xiàn)了不同以及現(xiàn)在的

8、集成電路設(shè)計(jì)遇到了哪些新的挑戰(zhàn)？未來，集成電路將如何發(fā)展？Integration reduces device size（減小尺寸）Laptop, iPod, mp3, cellphone, .Integration improves the design（提高性能）higher speed; lower power consuption;more reliable.Integration reduces manufacturing cost（降低成本）BOM (Board of Materials) cost reducesMass IC production reduces costDes

9、ign, fab, applicationEducationSoftwareCommunication/NetworkingFab cost: $2-$3 billionDriving force of world economyLarge investment: fab, packaging, design, EDAPentium 4 “Northwood”55M transistors / 2-2.5GHzL=0.13mGordon Moore Intel Founder“The number of transistors on a chip doubled every 18 to 24

10、months.”16151413121110987654321019591960196119621963196419651966196719681969197019711972197319741975LOG2 OF THE NUMBER OFCOMPONENTS PER INTEGRATED FUNCTIONElectronics, April 19, 1965.Gordon MooreIntel Co-Founder and Chairmain EmeritusImage source: Intel Corporation Electronic system in cars.Electron

11、ic financial system: e-banking,e-money, e-stock, RFID lablePersonal computing/entertainmentMedical electronic systems.Internet: routers, firewalls, servers, storagesElectronic library (Google, .)DVD R/W, HDTV, Interactive TVIn general, consumer electronicsetc .qComplexity: Multi-million transistors

12、on a single chip (smaller size/faster speed)qMultiple and conflicting specifications for high performance (power/speed/throughput)qCompetition: Short design timeqDesign Tools: Multiple tools involved, Complex design flowAnalog BasebandDigital Baseband(DSP + MCU)PowerManagementSmall Signal RFPowerRF

13、Layout designers Circuit designers (Digital/Analog/RF) Architects Test/Verification engineers Fabrication engineers System designers (SoC) CAD tool programmers Embedded System developers Software programmersFirst transistorBell Labs, 1947J. Bardeen, W. Shockley, and W. Brattain (1956 Nobel prize Lau

14、reate)19581958年年 J. KilbyJ. Kilby（TITI）研制成功第一個(gè)集成電路）研制成功第一個(gè)集成電路19591959年年 R. NoyceR. Noyce（FairchildFairchild）第一個(gè)利用平面工藝制）第一個(gè)利用平面工藝制成集成電路成集成電路The First Integrated Circuits Bipolar logic1960sECL 3-input GateMotorola 1966First commercial IC logic gates Fairchild 1960TTL 1962 into the 1990sECL 1974 into

15、the 1980s19702300 transistors1 MHz operationPentium 4 “Northwood” Commercial Production: Year 2001L=0.13m 6ML Cu Low-kFC-PGA2MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935CMOS 1960s, but plagued with manufacturing problems (used in watches due to their power limitations)P

16、MOS in 1960s (calculators)NMOS in 1970s (4004, 8080) for speedCMOS in 1980s preferred MOSFET technology because of power benefitsBiCMOS, Gallium-Arsenide, Silicon-GermaniumSOI, Copper-Low K, strained silicon, High-k gate oxide.Source: ISSCC 2003 G. Moore “No exponential is forever, but forever can b

17、e delayed”1.8 Ghz58 M118 mm2Apple Power G5, the fastestPC in 2003, has dual PPC 970CPU MicroprocessorASIC (Application Specific IC) Freq(HZ)TransistorsDie sizemm2Power DateServerIBM Power 4+1.7G180M267N/A2003Itanium 21.5G410M374130W2003IBM Power 5 2G276M 389 N/A 2004/2PCIBM Power PC970 1.8G58M11842W

18、2003/6Pentium 43.2G55M13182W2003/6AMD Athlon 642.2G105M19289W2003/9Pentium 4 (Prescott)3.4G125M112103W2004/2 Pentium 4 180 nm (2001) 1.7 G Hz 42 M transistors 217 mm2 Pentium 4 130 nm (2003) 3.2G Hz 55 M Transistors 131 mm2 Pentium 4 90 nm (2004) 3.4 Hz 125 M Transistors 112 mm2 Pentium on 65nm (200

19、5/2006) 250 Million Pentium on 45nm (2007) 400 to 500 Million (All use 0.13 um technology except Pentium 4 Prescott, which uses 90 nm tech)300mm wafer and Pentium 4 IC. Photos courtesy of Intel. “Microscopic Problems” Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturabili

20、ty Power Dissipation Clock distribution. “Macroscopic Issues” Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP Availability systems on a chip (SoC) Predictability etc.OutInVDDPMOSNMOS95%工程的藝術(shù)vMay be part of larger product design.vMajor levels of abstraction:specification archi

21、tecture logic design circuit design layout designFabless DesignHousesEDAToolsCompaniesDesignServiceCompaniesLibrary & IPProvidersDedicated IC Manufacturers (Foundry)PostPost: :EDA: Electronic Design AutomationIP: silicon Intellectual PropertyIDM: Integrated Device ManufacturerIntegratedservicePa

22、ckaging & Testing HousesFull Custom Design FlowCircuit is created by composing a transistor netlistSPICE simulation is performed to verify the circuitKnown as “capture-and-simulate” paradigmLayout is mostly done manuallyPopular for high-performance microprocessors & memoriesCell-Based Synthe

23、sis FlowDesign is first described by Hardware Description Language (e.g., Verilog and VHDL)Based on a cell library, netlist is created by synthesis toolsKnown as “describe-and-synthesize” paradigmLayout can be done through automatic toolsBlock Specification(Finite State Machine,Arithmetic Expression

24、,Boolean Expression)Logic Design Gate-Level Netlist Transistor NetlistTechnology MappingSPICE SimulationSPICEModelLayout Design LayoutLayoutRulesDesign Rule Checking (DRC)Layout vs. Schematic Check (LVS)Parasitic (or wiring) RC extractionPost-Layout SPICE SimulationCheck if SPEC is met ?If yes, done

25、.Otherwise, go back to optimize the designFunctionalityOne-bit binary full-adderTechnology1 mm n-well CMOS technologySpeedInput to output delay 5 ns Area 3000 mm2Power Dissipation exactly one of A, B,C is 1Technology mappingMany simple AND OR gates are merged into a complex gate (or a cell in the ce

26、ll library)Transistor aspect ratiopMOS (W/L) is usually larger than nMOS (W/L), e.g., 2:1xyxyx = (AB+BC+CA)y = (A+B+C) x + ABC)Post-layout SPICE simulationincludes the “parasitic resistance & capacitance”is more accurate than the pre-layout simulation (pre-sim)Ratio of channel widths2:1Propagati

27、on time tPHL or tPLH as defined aboveLow-to-high propagation time （傳播延時(shí)） tPLH = 8.2 ns ! Got to go back to optimize the design !C (Carry_in)SumTransistor Sizingchanges the aspect ratios (W/L) of selected transistorsA larger aspect ratio may lead to a higher speedWire Sizing is also more recently proposedPropagation Delay 5 ns !A/DPLAI/OcompRAMMetal1ViaMetal2I/O PadRandom logic(standardcell design)Architecture designSystem-level integrationlayoutNo violationMemorymoduleFunctionalmo