基于-Verilog的數(shù)字密碼鎖設計

1、 課程設計報告課程設計題目：基于Verilog的數(shù)字密碼鎖設計 學 號：201520070209學生姓名：尹景興專 業(yè)：通信工程班 級：1521301指導教師：鐘凱 2018年 1月 12 日目 錄一、課程設計內容- 1 -二、實現(xiàn)思路- 1 -1.解鎖過程- 1 -2.報警過程- 1 -3.重置密碼過程- 1 -三、實現(xiàn)程序- 2 -四、仿真驗證- 5 -1.解鎖過程- 5 -2.報警過程- 6 -3.重置密碼過程- 8 -五、設計心得- 11 - 一、 課程設計內容設計一個4位串行數(shù)字密碼鎖，要求如下：1. 開鎖密碼為4位二進制，當輸入密碼與鎖內給定的密碼一致時，方可開鎖。否則進入“錯誤”

2、狀態(tài)，發(fā)出報警信號。2. 鎖內的密碼可調。3. 串行數(shù)字密碼鎖的報警，直到按下復位開關，才停下。此時，數(shù)字密碼鎖又自動等待下一個開鎖狀態(tài)。二、 實現(xiàn)思路1. 解鎖過程密碼鎖出廠之前預設一個初始密碼，在本課程設計中將其預設為0101。在密碼鎖上鎖狀態(tài)下,輸入正確密碼，密碼鎖打開。2. 報警過程當輸入的密碼與鎖內密碼不一致時，蜂鳴器響起，直到按下取消按鍵，蜂鳴器才停止鳴叫。3. 重置密碼過程重置密碼時，需先驗證原密碼是否正確。當輸入原密碼正確，才可以輸入新密碼，設置新密碼為鎖內密碼。三、 實現(xiàn)程序module coded_lock(clk,in,set,pause,value1,value2,st

3、ore,bee,status,temp_set,ook); input clk,in,set,pause; output reg bee = 0; output reg status = 0; output reg temp_set = 0; output reg ook = 0; output reg3:0 value1; output reg3:0 value2; output reg3:0 store; reg en = 1; reg2:0 i = 0; reg2:0 j = 0; reg2:0 k = 0; reg2:0 count1 = 0; reg2:0 count2 = 0; r

4、eg2:0 count3 = 0; reg3:0 keynum = 4b0101; always (posedge clk) begin if(set = 1) fork temp_set = 1; value1 = 4bxxxx; value2 = 4bxxxx; store = 4bxxxx; i = 0; j = 0; k = 0; ook = 0; count1 = 0; count2 = 0; count3 = 0; join end always (posedge clk) begin if(temp_set = 0) begin case(en,in) 2b11: begin v

5、alue1i = 1b1; i = i + 1; count1 = count1 + 1;end 2b10: begin value1i = 1b0; i = i + 1; count1 = count1 + 1;end endcase end end always (posedge clk) begin if(count1 = 4) begin if(value1 = keynum) status = 1; else bee = 1; i = 0; count1 = 0; value1 = 4bxxxx; end end always (posedge clk) begin if(pause

6、 = 1) bee = 0; end always (posedge clk) begin if(temp_set = 1 & ook = 0) begin case(en,in) 2b11: begin value2j = 1b1; j = j + 1; count2 = count2 + 1;end 2b10: begin value2j = 1b0; j = j + 1; count2 = count2 + 1;end endcase end end always (posedge clk) begin if(count2 = 4) begin if(value2 = keynum) o

7、ok = 1; j = 0; count2 = 0; value2 = 4bxxxx; end end always (posedge clk) begin if(ook = 1) begin case(en,in) 2b11: begin storek = 1b1; k = k + 1; count3 = count3 + 1;end 2b10: begin storek = 1b0; k = k + 1; count3 = count3 + 1;end endcase end end always (posedge clk) begin if(count3 = 4) begin keynu

8、m = store; temp_set = 0; ook = 0; k = 0; count3 = 0; end end endmodule 四、 仿真驗證1. 解鎖過程測試平臺代碼：timescale 1ns/1nsmodule text; reg clk,set,pause; reg in; wire bee,status,ook; wire3:0 value1,value2; wire3:0 store; wire temp_set; coded_lock temp(.clk(clk),.in(in),.set(set),.pause(pause),.bee(bee),.ook(ook)

9、,.status(status),.value1(value1),.value2(value2),.store(store),.temp_set(temp_set); always #10 clk = clk; initial fork clk = 0; in = 1bx; set = 0; pause = 0; join initial begin #123 in = 1b1; #23 in = 1bx; #45 in = 1b0; #23 in = 1bx; #45 in = 1b1; #23 in = 1bx; #45 in = 1b0; #23 in = 1bx; end endmod

10、ule 如圖，當輸入預設密碼0101時，圖中status由0變?yōu)?，表示密碼鎖打開。2. 報警過程測試平臺代碼：timescale 1ns/1nsmodule text3; reg clk,set,pause; reg in; wire bee,status,ook; wire3:0 value1,value2; wire3:0 store; wire temp_set; coded_lock temp3(.clk(clk),.in(in),.set(set),.pause(pause),.bee(bee),.ook(ook),.status(status),.value1(value1),.

11、value2(value2),.store(store),.temp_set(temp_set); always #10 clk = clk; initial fork clk = 0; in = 1bx; set = 0; pause = 0; join initial begin #123 in = 1b1; #23 in = 1bx; #45 in = 1b1; #23 in = 1bx; #45 in = 1b0; #23 in = 1bx; #45 in = 1b0; #23 in = 1bx; #123 pause = 1; #23 pause = 0; end endmodule

12、如下圖，當輸入密碼0011時，與鎖內密碼不一致，bee由0變?yōu)?，表示蜂鳴器響起。當按下pause按鈕時，bee由1變?yōu)?，表示蜂鳴器停止鳴叫。3. 重置密碼過程測試平臺代碼：timescale 1ns/1nsmodule text2; reg clk,set,pause; reg in; wire bee,status,ook; wire3:0 value1,value2; wire3:0 store; wire temp_set; coded_lock temp2(.clk(clk),.in(in),.set(set),.pause(pause),.bee(bee),.ook(ook),.

13、status(status),.value1(value1),.value2(value2),.store(store),.temp_set(temp_set); always #10 clk = clk; initial fork clk = 0; in = 1bx; set = 0; pause = 0; join initial begin #123 set = 1; #21 set = 0; #123 in = 1b1; #21 in = 1bx; #45 in = 1b0; #21 in = 1bx; #45 in = 1b1; #21 in = 1bx; #45 in = 1b0;

14、 #21 in = 1bx; #125 in = 1b0; #21 in = 1bx; #45 in = 1b1; #21 in = 1bx; #45 in = 1b0; #21 in = 1bx; #45 in = 1b1; #21 in = 1bx; #125 in = 1b0; #21 in = 1bx; #45 in = 1b1; #21 in = 1bx; #45 in = 1b0; #21 in = 1bx; #45 in = 1b1; #21 in = 1bx;end endmodule 如下圖，當正確輸入預設密碼0101時，ook由0變?yōu)?，表示可以更改密碼，更改密碼為1010

15、。接著，輸入新密碼1010，status由0變?yōu)?，表示密碼鎖被新密碼打開，如下圖。五、 設計心得通過這次課程設計，我更深入熟悉了Verilog編程的各個過程和原理，并且，成功地做出了一個產品的簡化模型極大地挺高了我的學習興趣。當然，設計過程中也遇到了各種問題和困難，我極力克服，過后感覺受益匪淺。我會再接再厲的。Bingo! 東華理工大學課程設計評分表學生姓名：尹景興 班級：1521301 學號：201520070209課程設計題目：基于Verilog的數(shù)字密碼鎖設計 項目內容滿分實 評選題能結合所學課程知識、有一定的能力訓練。符合選題要求（5人一題）10工作量適中，難易度合理10能力水平能熟練應用所學知識，有一定查閱文獻及運用文獻資料能力10理論依據(jù)充分，數(shù)據(jù)準確，公式推導正確10能應用計算機軟件進行編程、資料搜集錄入、加工、排版、制圖等10能體現(xiàn)創(chuàng)造性思維，或有獨特見解10成果質量總體設計正確、合理，各項技術指標符合要