MIPI__協(xié)議詳細(xì)介紹ppt課件

1、 MIPIMIPI Protocol IntroductionMIPI Development Team 2010-9-21;.What is MIPI?What is MIPI?v MIPI stands for Mobile Industry Processor Interface MIPI Alliance is a collaboration of mobile industry leaders. Objective to promote open standards for interfaces to mobile application processors. Intends to

2、 speed deployment of new services to mobile users by establishing Spec.v Board Members in MIPI Alliance Intel, Motorola, Nokia, NXP,Samsung, ST, TIWhat is MIPI?What is MIPI?v MIPI Alliance Specification for display DCS (Display Command Set) DCS is a standardized command set intended for command mode

3、 display modules. DBI, DPI (Display Bus Interface, Display Pixel Interface) DBI：Parallel interfaces to display modules having display controllers and frame buffers. DPI：Parallel interfaces to display modules without on-panel display controller or frame buffer. DSI, CSI (Display Serial Interface, Cam

4、era Serial Interface) DSI specifies a high-speed serial interface between a host processor and display module. CSI specifies a high-speed serial interface between a host processor and camera module. D-PHY D-PHY provides the physical layer definition for DSI and CSI.DSI LayersDSI LayersDCS specDSI sp

5、ecD-PHY specOutlineOutlinev D-PHY Introduction Lane Module, State and Line levels Operating Modes Escape Mode System Power States Electrical Characteristics SummaryIntroduction for D-PHYv D-PHY describes a source synchronous, high speed, low power, low cost PHYv A PHY configuration contains A Clock

6、Lane One or more Data Lanesv Three main lane types Unidirectional Clock Lane Unidirectional Data Lane Bi-directional Data Lanev Transmission Mode Low-Power signaling mode for control purpose：10MHz (max) High-Speed signaling mode for fast-data traffic：80Mbps 1Gbps per Lanev D-PHY low-level protocol s

7、pecifies a minimum data unit of one byte A transmitter shall send data LSB first, MSB last.v D-PHY suited for mobile applications DSI：Display Serial Interface A clock lane, One to four data lanes. CSI：Camera Serial InterfaceTwo Data Lane PHY ConfigurationTwo Data Lane PHY ConfigurationLane Modulev P

8、HY consists of D-PHY (Lane Module)v D-PHY may contain Low-Power Transmitter (LP-TX) Low-Power Receiver (LP-RX) High-Speed Transmitter (HS-TX) High-Speed Receiver (HS-RX) Low-Power Contention Detector (LP-CD)v Three main lane types Unidirectional Clock Lane Master：HS-TX, LP-TX Slave：HS-RX, LP-RX Unid

9、irectional Data Lane Master：HS-TX, LP-TX Slave：HS-RX, LP-RX Bi-directional Data Lane Master, Slave：HS-TX, HS-RX,LP-TX, LP-RX, LP-CDUniversal Lane Module ArchitectureUniversal Lane Module ArchitectureLane States and Line Levels The two LP-TXs drive the two Lines of a Lane independently and single-end

10、ed. Four possible Low-Power Lane states (LP-00, LP-01, LP-10, LP-11) A HS-TX drives the Lane differentially. Two possible High Speed Lane states (HS-0, HS-1) During HS transmission the LP Receivers observe LP-00 on the Lines Line Levels (typical) LP：01.2V HS：100300mV (Swing：200mV) Lane States LP-00,

11、 LP-01, LP-10, LP-11 HS-0, HS-1Operating Modes There are three operating modes in Data Lane Escape mode, High-Speed (Burst) mode and Control mode Possible events starting from the Stop State of control mode Escape mode request (LP-11LP-10LP-00LP-01LP-00) High-Speed mode request (LP-11LP-01LP-00) Tur

12、naround request (LP-11LP-10LP-00LP-10LP-00)Escape ModeEscape Modev Escape mode is a special operation for Data Lanes using LP states. With this mode some additional functionality becomes available：LPDT, ULPS, Trigger A Data Lane shall enter Escape mode via LP-11LP-10LP-00LP-01LP-00 Once Escape mode

13、is entered, the transmitter shall send an 8-bit entry command to indicate the requested action. Escape mode uses Spaced-One-Hot Encoding. means each Mark State is interleaved with a Space State (LP-00). Send Mark-0/1 followed by a Space to transmit a zero-bit/ one-bit A Data Lane shall exit Escape m

14、ode via LP-10LP-11v Ultra-Low Power State During this state, the Lines are in the Space state (LP-00) Exited by means of a Mark-1 state with a length TWAKEUP(1ms) followed by a Stop state.Escape ModeEscape ModeClock Lane Ultra-Low Power StateClock Lane Ultra-Low Power Statev A Clock Lane shall enter

15、 ULPS via LP-11LP-10LP-00v exited by means of a Mark-1 with a length TWAKEUP followed by a Stop State LP-10 TWAKEUP LP-11 The minimum value of TWAKEUP is 1msHigh-Speed Data TransmissionHigh-Speed Data Transmissionv The action of sending high-speed serial data is called HS transmission or burst.v Sta

16、rt-of-Transmission LP-11LP-01LP-00SoT(0001_1101) HS Data Transmission Burst All Lanes will start synchronously But may end at different times The clock Lane shall be in High-Speed mode, providing a DDR Clock to the Slave sidev End-of-Transmission H Toggles differential state immediately after last p

17、ayload data bitv and keeps that state for a time THS-TRAILHigh-Speed Clock TransmissionHigh-Speed Clock Transmissionv Switching the Clock Lane between Clock Transmission and LP Mode A Clock Lane is a unidirectional Lane from Master to Slave In HS mode, the clock Lane provides a low-swing, differenti

18、al DDR clock signal. the Clock Burst always starts and ends with an HS-0 state. the Clock Burst always contains an even number of transitionsSummary for D-PHYSummary for D-PHYv Lane Module, Lane State and Line Levels Lane Module：LP-TX, LP-RX, HS-TX, HS-RX, LP-CD Lane States：LP-00, LP-01, LP-10, LP-1

19、1, HS-0, HS-1 Line Levels (typical)：LP：01.2V, HS：100300mV (Swing：200mV)v Operating Modes Escape Mode entry procedure ：LP-11LP-10LP-00LP-01LP-00Entry Code LPD (10MHz) Escape Mode exit procedure：LP-10LP-11 High Speed Mode entry procedure：LP-11LP-01LP-00SoT(00011101) HSD (80Mbps 1Gbps) High Speed Mode

20、exit procedure：EoTLP-11 Control Mode - BTA transmission procedure：LP-11LP-10LP-00LP-10LP-00 Control Mode - BTA receive procedure：LP-00LP-10LP-11v System Power States Low-Power mode, High-Speed mode, Ultra-Low Power modev Fault Detection Contention Detection (LP-CD), Watchdog Timer, Sequence Error De

21、tection (Error Report)v Global Operation Timing Parameter Clock Lane Timing, Data Lane Timing Other Timing Initialization, BTA, Wake-Up from ULPSv Electrical Characteristics HS-RX, LP-RX, LP-TX, LP-CD, Pin characteristic, Clock signal, Data-Clock timing DC and AC characteristicOutlineOutlinev DSI In

22、troduction Lane Distributor/Merger Conceptual Packet Structure Data Transmission Way Processor-Sourced Packets Peripheral-Sourced Packets Reverse-Direction LP Transmission Video Mode SummaryIntroduction for DSIIntroduction for DSIv DSI is a Lane-scalable interface for increased performance. One Cloc

23、k Lane / One to Four Data Lanesv DSI-compliant peripherals support either of two basic modes of operation Command Mode (Similar to MPU IF) Data Lane 0：bidirectional For returning data, ACK or error report to host Additional Data Lanes：unidirectional. Video Mode (Similar to RGB IF) Data Lane 0：bidire

24、ctional or unidirectional; Additional Data Lanes：unidirectional. Video data should only be transmitted using HS mode.v Transmission Mode High-Speed signaling mode Low-Power signaling mode Forward/Reverse direction LP transmissions shall use Data Lane 0 only For returning data, DSI-compliant systems

25、shall only use Data Lane 0 in LP Modev Packet Types Short Packet：4 bytes (fixed length) Long Packet：665541 bytes (variable length)Two Data Lanes HS Transmission ExampleTwo Data Lanes HS Transmission ExampleData Transmission Wayv Separate Transmissionsv Separate Transmissionsv KEY: LPS Low Power Stat

26、e SP Short Packet SoT Start of Transmission LgP Long Packet EoT End of TransmissionShort Packet StructureShort Packet Structurev Packet Header (4 bytes) Data Identifier (DI) * 1byte： Contains the Virtual Channel7:6 and Data Type5:0. Packet Data * 2byte：Length is fixed at two bytes Error Correction C

27、ode (ECC) * 1byte：allows single-bit errors to be corrected and 2-bit errors to be detected.v Packet Size Fixed length 4 bytesv The first byte of any packet is the DI (Data Identifier) byte. DI7:6：These two bits identify the data as directed to one of four virtual channels. DI5:0：These six bits speci

28、fy the Data Type.Long Packet StructureLong Packet Structurev Packet Header (4 bytes) Data Identifier (DI) * 1byte：Contains the Virtual Channel7:6 and Data Type5:0. Word Count (WC) * 2byte：defines the number of bytes in the Data Payload. Error Correction Code (ECC) * 1byte：allows single-bit errors to

29、 be corrected and 2-bit errors to be detected.v Data Payload (065535 bytes) Length = WC bytesv Packet Footer (2 bytes)：Checksum If the payload has length 0, then the Checksum calculation results in FFFFh If the Checksum isnt calculated, the Checksum value is 0000hv Packet Size 4 + (065535) + 2 = 6 6

30、5541 bytesData Types for Processor-sourced PacketsData Types for Processor-sourced PacketsError Correction CodeError Correction Codev P7 = 0v P6 = 0v P5 = D10D11D12D13D14D15D16D17D18D19D21D22D23v P4 = D4D5D6D7D8D9D16D17D18D19D20D22D23v P3 = D1D2D3D7D8D9D13D14D15D19D20D21D23v P2 = D0D2D3D5D6D9D11D12D

31、15D18D20D21D22v P1 = D0D1D3D4D6D8D10D12D14D17D20D21D22D23v P0 = D0D1D2D4D5D7D10D11D13D16D20D21D22D23ChecksumChecksumv unsigned char xx = 0 x01,0 x5a,0 x5a,0 x03,0 x08,0 x2A, 0 x00,0 x01 ,0 x00,0 xF8,0 x00,0 xF6,0 x57,0 x00,0X00,0 xE5;v typedef unsigned short U16;v typedef unsigned char U8;v U16 CRC_

32、test;v U16 crc16_update(U16 crc, U8 a);v int main()v v U16 crc,i;v crc = 0 xFFFF;v for (i=0; i1; i+) crc = crc16_update(crc, xxi);v CRC_test = crc;v v U16 crc16_update(U16 crc, U8 a) v v int i;v crc =a;v for (i = 0; i 1) 0 x8408;v else crc = (crc 1);v v return crc;v Peripheral-to-Processor LP Transm

33、issionsv Detailed format description Packet structure for peripheral-to-processor transactions is the same as for the processor-to-peripheral directionv For a single-byte read response, valid data shall be returned in the first byte The second byte shall be sent as 00hv If the peripheral does not su

34、pport Checksum it shall return 0000hPeripheral-to-Processor LP Transmissionsv Peripheral-to-processor transactions are of four basic types Tearing Effect (TE)：trigger message (BAh) Acknowledge：trigger message (84h) Acknowledge and Error Report：short packet (Data Type is 02h) Response to Read Request：short pac