北郵數(shù)字電路綜合實(shí)驗(yàn)報(bào)告

1、數(shù)字電路綜合實(shí)驗(yàn)報(bào)告簡(jiǎn)易智能密碼鎖一、實(shí)驗(yàn)課題及任務(wù)要求密碼輸入正設(shè)計(jì)并實(shí)現(xiàn)一個(gè)數(shù)字密碼鎖，密碼鎖有四位數(shù)字密碼和一個(gè)確認(rèn)開(kāi)鎖按鍵， 確，密碼鎖打開(kāi)，密碼輸入錯(cuò)誤進(jìn)行警示。 基本要求：1、 密碼設(shè)置：通過(guò)鍵盤(pán)進(jìn)行4位數(shù)字密碼設(shè)定輸入，在數(shù)碼管上顯示所輸入數(shù)字。 通過(guò)密碼設(shè)置確定鍵（BTN鍵）進(jìn)行鎖定。2、 開(kāi)鎖：在閉鎖狀態(tài)下，可以輸入密碼開(kāi)鎖， 且每輸入一位密碼， 在數(shù)碼管上顯示“-”, 提示已輸入密碼的位數(shù)。輸入四位核對(duì)密碼后，按“開(kāi)鎖”鍵，若密碼正確則系統(tǒng)開(kāi)鎖，若 密碼錯(cuò)誤系統(tǒng)仍然處于閉鎖狀態(tài)，并用蜂鳴器或led閃爍報(bào)警。3、 在開(kāi)鎖狀態(tài)下，可以通過(guò)密碼復(fù)位鍵 （BTN鍵）來(lái)清除密碼，恢復(fù)

2、初始密碼“0000”。 閉鎖狀態(tài)下不能清除密碼。4、用點(diǎn)陣顯示開(kāi)鎖和閉鎖狀態(tài)。 提高要求：，同時(shí)1、輸入密碼數(shù)字由右向左依次顯示，即：每輸入一數(shù)字顯示在最右邊的數(shù)碼管上 將先前輸入的所有數(shù)字向左移動(dòng)一位。2、密碼鎖的密碼位數(shù)（46位）可調(diào)。3、自擬其它功能。二、系統(tǒng)設(shè)計(jì)2.1系統(tǒng)總體框圖22邏輯流程圖2.4分塊說(shuō)明數(shù)碼管模塊，點(diǎn)陣模塊，報(bào)警模塊，防抖模塊，控程序主要分為6個(gè)模塊：鍵盤(pán)模塊，制模塊。以下進(jìn)行詳細(xì)介紹。1.鍵盤(pán)模塊然后獲取其鍵值，并對(duì)其進(jìn)行編碼，從而進(jìn)行按鍵本模塊主要完成是 4 X 4鍵盤(pán)掃描， 的識(shí)別，并將相應(yīng)的按鍵值進(jìn)行顯示。鍵盤(pán)掃描的實(shí)現(xiàn)過(guò)程如下：對(duì)于 4X 4鍵盤(pán)，通常連接

3、為 4行、4列，因此要識(shí)別按鍵， 只需要知道是哪一行和哪一列即可，為了完成這一識(shí)別過(guò)程，我們的思想是，首先固定輸出高電平，在讀入輸出的行值時(shí)，通常高電平會(huì)被低電平拉低，當(dāng)當(dāng)前位置為高電平“1”時(shí),沒(méi)有按鍵按下，否則，如果讀入的4行有一位為低電平，那么對(duì)應(yīng)的該行肯定有一個(gè)按鍵按4列為高電平，然后 那么肯定對(duì)應(yīng)的那一列有X789X456X123XX0x（X為無(wú)效按鍵）*消抖鍵盤(pán)譯碼按鍵儲(chǔ)存鍵盤(pán)掃描下，這樣便可以獲取到按鍵的行值。同理，獲取列值也是如此，先輸出 在輸出4行為低電平，再讀入列值，如果其中有哪一位為低電平， 按鍵按下。由此可確定按鍵位置。2數(shù)碼管模塊本實(shí)驗(yàn)采用六位七段共陰極數(shù)碼管，通過(guò)選

4、通 6個(gè)位選管腳，向相應(yīng)的10 口送低電平 來(lái)點(diǎn)亮其中任何一位數(shù)碼管， 因?yàn)楝F(xiàn)在采用四位密碼鎖， 所以只是用了其中四個(gè)， 最高位兩 位數(shù)碼管位選全部置 1.如下附上7段共陰極數(shù)碼管真值表3.點(diǎn)陣模塊點(diǎn)陣模塊，共由模式和閉鎖模式顯示不同的圖案, 在有圖案下落處的小方格里填上8*8*2個(gè)發(fā)光二極管組成,行低電平有效，列高電平有效。要求在開(kāi)鎖則先將要顯示的每幅圖像畫(huà)8*8個(gè)小方格的矩形框中，再“1”，無(wú)圖案處填上“ 0”，這樣就形成了與圖案所對(duì)應(yīng)的二巴輸出字形Fd1111110rm 1 10110000111101101一 0匚111100130110011011011C1011111r111000

5、011111111廠11111110111 -1 .0,反之亦進(jìn)制數(shù)據(jù)在該矩形框上的分布。當(dāng)閉鎖時(shí)以紅色點(diǎn)陣顯示，此時(shí)綠色點(diǎn)陣全部置 然。4扌報(bào)警模塊當(dāng)報(bào)警程序被調(diào)用，蜂鳴器輸出高電平進(jìn)行報(bào)警，表示輸入密碼錯(cuò)誤5. 防抖按鍵輸入只有為15ms以上的高電平時(shí)才會(huì)讀出按鍵值從而消除電路中的抖動(dòng)。6. 控制中心lockmode='1表示關(guān)鎖，此時(shí)點(diǎn)陣顯示落鎖，按任何鍵都不會(huì)顯示密碼，清零或者開(kāi)鎖，在此時(shí)輸入密碼 kwei從0開(kāi)始不斷加1,輸入的密碼位數(shù)在數(shù)碼管上依次左移，當(dāng)輸入密 碼m與寄存器中預(yù)設(shè)密碼 mm相同時(shí)，按下確認(rèn)鍵 btn2切換為開(kāi)鎖狀態(tài)，lockmode=0 ,此 時(shí)按下btn

6、1表示清零，恢復(fù)為初始密碼0000,按set鍵寄存器內(nèi)密碼，按下btnioc切換為關(guān)鎖狀態(tài)。三、仿真波形分析在QUARTUS2中應(yīng)用系統(tǒng)自帶的功能進(jìn)行波形仿真，這里采用了分模塊仿真。主程序仿真在主要功能程序方面波形如下，在初始化模式按下set鍵系統(tǒng)進(jìn)入修改密碼狀態(tài)，setmode波形顯示高電平。為仿真方便，僅使kbin （即行輸入信號(hào)）在 1011和1111兩個(gè)狀態(tài)下相互轉(zhuǎn)換，在不同的kbout （即列掃描輸出信號(hào)）下分別對(duì)應(yīng)4、5、6、7四個(gè)數(shù)字，故密碼寄存器mx為輸入的修改后的密碼。按下btn2 （確認(rèn)鍵）確認(rèn)密碼后，setmode變?yōu)榈碗娖?，即修改密碼狀態(tài)結(jié)束。按下btn1時(shí)清零，密碼寄

7、存器取值還原為 0000,至此均為開(kāi)鎖狀態(tài)下的操作，lockmode 一直為低電平。按下閉鎖鍵btnioc后，lockmode從0跳變到1,由此進(jìn)入閉鎖模式。按鍵消抖模塊仿真當(dāng)按下鍵時(shí)得到的高電平為輸入X,持續(xù)一定時(shí)間后方可輸出一個(gè)高電平，而無(wú)論按下的時(shí)間多長(zhǎng)，都只輸出一個(gè)高電平y(tǒng)，從而實(shí)現(xiàn)消除按鍵電路中的抖動(dòng)。ir T. th爭(zhēng)6弘3弓甲和A】L* I甲墜呷15 CT5 Q5_rLJ"m_n_n_n_ru"T_rT_p_n_rLJLTT_n_rm_rm_n_rLjJ'I""!""3,分頻模塊仿真為仿真方便，改變分頻比。原程序

8、在50Mhz時(shí)鐘輸入下，輸出分別為1Mhz、200hzlOOOhz、500hz,分別用于鍵盤(pán)掃描、消抖模塊輸入、點(diǎn)陣掃描以及數(shù)碼管掃描。Te u甘ay_wiitivu.t£III01 utIrtfaVir7阿JJl-ta-iler數(shù)碼管模塊仿真第i位選通時(shí)，smgzf為mi的七段由smgcatout輸出可以看出低四位數(shù)碼管依次選通。數(shù)碼管的譯碼值。II?-*"'n：WWOTM 卜10如 丁"皿JMI 24SlZjHi 翡 HEtrtJ lfi*tViI p>E EE 3T.$S “'S.12 nxD E4cLkkELLcrb-ilenLrJM

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12、mraomTOomwowioTOmjTOfnwiowionmMOfrjurawjioni四、源程序頂層文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity lock isport (clk : in std_logic;setmode:out std_logic; lockmode:out std_logic; set:in std_logic;bt n1,bt n2,bt nloc:in std_logic;smgzf: out std_logic_vector(6 dow

13、nto 0); smgcatout:out std_logic_vector(5 dow nto 0); kbin: instd_logic_vector(3 dow nto 0);kbout: buffer std_logic_vector(3 dow nto 0); dzrow,dzcolr,dzcolg: out std_logic_vector(7 dow nto 0); fmq: out std_logic);end lock;setm: std_logic; lockm: std_logic; Ibj: std_logic;architecture behave of lock i

14、ssig nalsig nalsig nal sig nal Ikwei: in teger range 0 to 4;sig nal Im1,lm2,lm3,lm4:i nteger range 0 to 9;-1MHZ-200Hz-1000Hz-500Hz鍵盤(pán)模塊sig nal clk_1: std_logic;sig nal clk_2: std_logic;sig nal clk_3: std_logic;sig nal clk_4: std_logic; component kb is port (clk : in std_logic;set:in std_logic;bt n1,b

15、t n2,bt nloc:in std_logic;kbin: in std_logic_vector(3 dow nto 0); kbout: buffer std_logic_vector(3 dow nto 0); bj:out std_logic;setmod:out std_logic; lockmod:out std_logic;kbwei:out in teger range 0 to 4;m1x,m2x,m3x,m4x:out in teger range 0 to 9);end component;component smg is數(shù)碼管顯示模塊port (clk : in s

16、td_logic;setmode:i n std_logic; lockmode:i n std_logic; kwei:i n in teger range 0 to 4; m1,m2,m3,m4:in in teger range 0 to 9; smgzf: out std_logic_vector(6 dow nto 0); smgcatout:out std_logic_vector(5 dow nto 0) );end component;component dz is 點(diǎn)陣模塊 port (clk : in std_logic;-set:in std_logic;lockmode

17、:i n std_logic;dzrow,dzcolr,dzcolg: out std_logic_vector(7 dow nto 0) );end component;報(bào)警模塊component alarm is -port (clk : in std_logic;bj:in std_logic;fmq: out std_logic)；end component;component fenpin is 分頻模塊po rt(clk: in std_logic;clk_out1: out std_logic; clk_out2: out std_logic; clk_out3: out std

18、_logic;clk_out4: out std_logic);end component;begina1: fenpinport ma p(clk=>clk,clk_out1=>clk_1,clk_out2=>clk_2, clk_out3=>clk_3,clk_out4=>clk_4);u1: kbport map(clk=> elk,set => set,btn1 =>bt n1,bt n2=>bt n2,bt nloc=>bt nioc,kbin=>kb in, kbout=>kbout, bj=>lbj,

19、setmod=>setm, lockmod=>lockm, kbwei=>lkwei, m1x=>lm1,m2x=>lm2,m3x=>lm3,m4x=>lm4);u2 :smgport map(clk => clk_4,setmode=>setm,lockmode=>lockm,kwei=>lkwei,m1=>lm1,m2=>lm2,m3=>lm3,m4=>lm4,smgzf=>smgzf,smgcatout=>smgcatout);u3 :dzportmap( clk=>clk_3,l

20、ockmode=>lockm ,dzrow=>dzrow, dzcolr=>dzcolg,dzcolg=>dzcolr );u4 :alarm port map( clk => clk, bj=>lbj, fmq=>fmq); setmode<=setm;lockmode<=lockm;en d;鍵盤(pán)模塊library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity kb isport (clk : in std_logic;set:in

21、 std_logic;bt n1,bt n2,bt nloc:in std_logic;kbin: in std_logic_vector(3 dow nto 0); kbout: buffer std_logic_vector(3 dow nto 0); bj:out std_logic;setmod:out std_logic;lockmod:out std_logic;kbwei:out in teger range 0 to 4; m1x,m2x,m3x,m4x:out in teger range 0 to 9 );end kb;architecture behave of kb i

22、ssig nal jpo ut:i nteger range 0 to 10;sig nal alarm:std_logic;sig nal tmp4: in teger range 0 to 2499999;sig nal clkfd: std_logic;sig nal m1,m2,m3,m4,mm1,mm2,mm3,mm4: in teger range 0 to 9;sig nal wei:i nteger range 0 to 3;sig nal kwei:i nteger range 0 to 4;sig nal setmode:std_logic; sig nal lockmod

23、e:std_logic;sig nal set1:std_logic; sig nal clear: std_logic;sig nal sure: std_logic; sig nal lock: std_logic;sig nal enfini sh: std_logic;sig nal btn 1_out, btn 2_out, btnio c_out, set_out: std_logic;sig nal clk_1: std_logic;-1MHzsig nal clk_2: std_logic;-200Hz component sca n ispo rt(clk_1: in std

24、_logic;clk_2: in std_logic;row: in std_logic_vector(3 dow nto 0); col: buffer std_logic_vector(3 dow nto 0); en_up: buffer std_logic;y: out in teger range 0 to 10);end component;component fenpin is po rt(clk: in std_logic;clk_out1: out std_logic;clk_out2: out std_logic;clk_out3: out std_logic;clk_ou

25、t4: out std_logic); end component;component debo unce is po rt(clk, x: in std_logic; y: out std_logic);end component;beginsetmod<=setmode;lockmod<=lockmode;bj<=alarm;kbwei<=kwei;m1x<=m1;m2x<=m2;m3x<=m3;m4x<=m4;u1: sca n port map( clk_1=>clk_1,clk_2=>clk_2,row=>kb in,

26、col=>kbout,en_up=>en, y=>jpo ut);u2:fenpin portmap (clk=>clk,clk_out1=>clk_1, clk_out2=>clk_2,clk_out3=>open, clk_out4=>open);u3: debo unce port map( clk=>clk_2, x=>bt n1, y=>bt n1_out);u4: debo unce port map( clk=>clk_2, x=>bt n2, y=>bt n2_out);u5: debo unc

27、e port map( clk=>clk_2, x=>bt nl oc, y=>bt nio c_out);u6: debo unce port map( clk=>clk_2, x=>set, y=>set_out);pro cess(clk)beginif(clk'eve nt and clk='1')the nif (tmp4=2499999) thentmp4<=0;clkfd <=not clkfd;elsetmp4 <=t mp 4+1;end if;end if;end pro cess;p roces

28、s(clk_1,e njpo ut)beginif(clk_1'eve nt and clk_1='1') then閉鎖狀態(tài)下輸入密碼并讀入按鍵值后存入mmif(lockmode='1')the n-wei<=0;if(jpo ut/=10)thenif(kwei=3)the n mm4<=jpo ut;kwei<=kwei+1; elsif(kwei=2)the n mm3<=j po ut;kwei<=kwei+1; elsif(kwei=1)the n mm2<=j po ut;kwei<=kwei+1;

29、elsif(kwei=0)the n mm1<=j po ut;kwei<=kwei+1;end if;end if ;if(sure='1')the n 確認(rèn)后判斷密碼是否正確the nif(mm1=m1)a nd(mm2=m2)a nd(mm3=m3)a nd(mm4=m4)lockmode<='0'alarm<='0'正確開(kāi)鎖else kwei<=0;alarm<='1'錯(cuò)誤報(bào)警end if; end if;else kwei<=0;if(lock='1')then

30、- lockmode<='1' else開(kāi)鎖狀態(tài)下-上鎖if(set1='1')then setmode<='1'-else setmode<='0'end if;if(clear='1') the n 清零m1<=0;m2<=0;m3<=0;m4<=0;-mm1<=0;mm2<=0;mm3<=0;mm4<=0; wei<=0;kwei<=0;alarm<='0'elsif(setmode='1')t

31、he nif(jpout/=10)then 修改密碼狀態(tài)下讀入按鍵值存入m并移位if(wei=0)the n m1<=m2;m2<=m3;m3<=m4; m4<=jpo ut;wei<=wei+1; elsif(wei=1)the n m1<=m2;m2<=m3;m3<=m4; m4<=jpo ut;wei<=wei+1; elsif(wei=2)the n m1<=m2;m2<=m3;m3<=m4; m4<=jpo ut;wei<=wei+1; elsif(wei=3)the n m1<=m2;m

32、2<=m3;m3<=m4; m4<=jpo ut;wei<=0;end if;end if;if(sure='1')the n setmode<='0'alarm<='0' end if;end if;end if;end if;end if;end pro cess;修改密碼確認(rèn)后結(jié)束修改密碼狀態(tài)pro cess(set,sure)begin if(clkfd'eve nt and clkfd='1')then if(set='1')the n set1<=

33、9;1'end if; if(sure='1')the n set1<='0'end if;end if;end p rocess;修改密碼鍵pro cess(bt n1) beginif(bt n仁'1')then清零鍵clear<='1' else clear<='0' end if; end pro cess;確認(rèn)鍵p rocess(bt n2)beginif(bt n2='1')the nsure<='1'else sure<='

34、0' end if;end pro cess;p rocess(bt nioc)begin閉鎖鍵if(bt nloc='1')then lock<='1'else lock<='0' end if;end pro cess;end;鍵盤(pán)掃描library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity sca n isport(clk_1: in std_logic;-高頻(for scan) 1Mhz clkout1 cl

35、k_2: in std_logic;-低頻(for debounee) 200hz clkout2 row: in std_logic_vector(3 dow nto 0);col: buffer std_logic_vector(3 dow nto 0);en_up: out std_logic;y: out in teger range 0 to 10);end sca n;architecture a of sca n issig nal en: std_logic; component debo unce is po rt(clk, x: in std_logic; y: out s

36、td_logic); end component;beginu1: debo unce port map( clk=>clk_2, x=>e n, y=>e n_up); p rocess(clk_1) begin列掃描if(clk_1'eve nt and clk_1='1') then if(e n='1') then col<="1000"elsecase col iswhe n "1110" => col<="1101"whe n "1101

37、" => col<="1011"whe n "1011" => col<="1110"whe n others => col<="1110" end case;end if;end if;end pro cess;p rocess(clk_1, col, row)beginif(clk_1'eve nt and clk_1='1') then case col iswhe n "1000"=>if(row(3) and

38、row(2) and row(1) and row(0)='1') then en <='0'end if;whe n "1110"=>case row is-when "1110" => y<="1111" whe n "1101" =>y<=1; en <='1' whe n "1011" =>y<=4;en <='1'whe n "0111" =&

39、gt;y<=7;en <='1'whe n others => y<=10;-1-4-7-5-8end case;whe n "1101"=>case row is-0-2whe n "1110" =>y<=0; en <='1' when "1101" =>y<=2; en <='1'when "1011" =>y<=5; en <='1' whe n "0

40、111" =>y<=8; en <='1'whe n others =>y<=10;end case;when "1011"=>case row is -when "1110" => y<="1111"when "1101" =>y<=3;en<='1'-3whe n "1011" =>y<=6;en<='1'-6whe n "0111"

41、; =>y<=9;en<='1'-9whe n others =>y<=10;end case;whe n others => n ull;end case;end if;end pro cess;end a;消抖library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity debo unce isport(clk, x: in std_logic; y: out std_logic);end debo unce;200hz低頻時(shí)鐘arc

42、hitecture a of debo unce istype state is(s0,s1,s2,s3,s4); sig nal p re_s, n ext_s: state;beginp rocess(clk)beginif(clk'eve nt and clk='1') then p re_s<=n ext_s;end if;end pro cess;個(gè)狀態(tài)p rocess( pre_s, x)- begincase pre_s iswhe n s0 =>if(x='1') the nn ext_s<=s1; else輸入為連續(xù)3

43、個(gè)或以上的高電平時(shí)，輸出一個(gè)高電平初始狀態(tài)s0n ext_s<=sO; end if;y<='0'whe n s1 =>if(x='1') the nn ext_s<=s2;elsen ext_s<=sO; end if;y<='0'whe n s2 =>if(x='1') the nn ext_s<=s3; elsen ext_s<=s0; end if;y<='0'連續(xù)3個(gè)高電平，輸出一個(gè)高電平3個(gè)以上高電平，不再繼續(xù)輸出高電平whe n s3 =&g

44、t;y<='1' n ext_s<=s4;whe n s4 =>y<='0'if(x='1') the nn ext_s<=s4; elsen ext_s<=s0; end if;end case;end pro cess;end a;分頻模塊library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity fenpin isport(clk: in std_logic;clk_out1: out std_lo

45、gic;clk_out2: out std_logic;clk_out3: out std_logic;clk_out4: out std_logic );end fenpin;architecture div of fenpin isconstant div1: integer:=24; -1Mhz，用于鍵盤(pán)掃描 constant div2: integer:=124999; -200hz，用于消抖 constant div3: integer:=24999;- -lOOOhz,用于點(diǎn)陣掃描 constant div4: integer:=49999; -500hz，用于數(shù)碼管掃描 sig

46、nal c1: in teger range 0 to div1;sig nal c2: in teger range 0 to div2;sig nal c3: in teger range 0 to div3;sig nal c4: in teger range 0 to div4;sig nal temp1: std_logic;sig nal temp2: std_logic;sig nal temp3: std_logic;sig nal temp4: std_logic;beginpro cess(clk)beginif(clk'eve nt and clk='1&

47、#39;) the n if(c1=div1) the ntemp1<=not temp1;c1<=0;elsec1<=c1+1;end if;if(c2=div2) the ntemp2<=not temp2; c2<=0;elsec2<=c2+1;end if;if(c3=div3) thentemp3<=not temp3; c3<=0;elsec3<=c3+1;end if;if(c4=div4) the ntemp4<=not temp4; c4<=0;elsec4<=c4+1;end if;end if;end

48、 pro cess;clk_out1<=te mp1;clk_out2<=tem p2;clk_out3<=tem p3;clk_out4<=te mp4;end div;數(shù)碼管library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity smg isport (clk : in std_logic;-500hz clkout4setmode:i n std_logic; lockmode:i n std_logic;-四位密碼的值編碼值kwei:i n in te

49、ger range 0 to 4; m1,m2,m3,m4:in in teger range 0 to 9;smgzf: out std_logic_vector(6 dow nto 0); smgcatout:out std_logic_vector(5 dow nto 0) );end smg;architecture behave of smg issig nal smgcat: in teger range 0 to 5;sig nal m1y,m2y,m3y,m4y:std_logic_vector(6 dow nto 0);begin位選碼pro cess(clk)beginif

50、(clk'eve nt and clk='1')then if (smgcat=5)the n smgcat<=0;else smgcat<=smgcat+1;end if;end if;end p rocess;pro cess(setmode,lockmode,smgcat)beginif(lockmode='0')the ncase smgcat is 輸入密碼值在數(shù)碼管顯示，從左到右whe n 0=>smgcatout<="110111"smgzf<=m1y;whe n 1=>smgcato

51、ut<="111011"smgzf<=m2y;whe n 2=>smgcatout<="111101"smgzf<=m3y;whe n 3=>smgcatout<="111110"smgzf<=m4y;whe n 4=>smgcatout<="111111"whe n 5=>smgcatout<="111111"end case;elsesmgzf<="0000001"輸入密碼在數(shù)碼管顯示if (k

52、wei=1)the n smgcatout<="111110"elsif (kwei=2)then smgcatout<="111100"elsif (kwei=3)then smgcatout<="111000"elsif (kwei=4)then smgcatout<="110000"else smgcatout<="111111"end if;end if;end pro cess;p rocess(m1)begincase m1 is七段數(shù)碼管真值表whe

53、n 0=>m1y<="1111110"whe n 1=>m1y<="0110000"whe n 2=>m1y<="1101101"whe n 3=>m1y<="1111001"whe n 4=>m1y<="0110011"whe n 5=>m1y<="1011011"whe n 6=>m1y<="1011111"when 7=>m1y<="111000

54、0"whe n 8=>m1y<="1111111"whe n 9=>m1y<="1111011"whe n others=>m1y<="0000000" end case;end p rocess;pro cess(m2)begincase m2 iswhe n 0=>m2y<="1111110"when 1=>m2y<="0110000"whe n 2=>m2y<="1101101"when

55、3=>m2y<="1111001"whe n 4=>m2y<="0110011"whe n 5=>m2y<="1011011"whe n 6=>m2y<="1011111"when 7=>m2y<="1110000"whe n 8=>m2y<="1111111"whe n 9=>m2y<="1111011" when others=>m2y<="000

56、0000" end case;end p rocess;p rocess(m3)begincase m3 is whe n 0=>m3y<="1111110" when 1=>m3y<="0110000"whe n 2=>m3y<="1101101"whe n 3=>m3y<="1111001"whe n 4=>m3y<="0110011"whe n 5=>m3y<="1011011"whe n

57、 6=>m3y<="1011111"when 7=>m3y<="1110000"whe n 8=>m3y<="1111111"whe n 9=>m3y<="1111011"when others=>m3y<="0000000" end case;end p rocess;p rocess(m4)begincase m4 iswhe n 0=>m4y<="1111110"when 1=>m4y<

58、="0110000"whe n 2=>m4y<="1101101"when 3=>m4y<="1111001"whe n 4=>m4y<="0110011"whe n 5=>m4y<="1011011"whe n 6=>m4y<="1011111"when 7=>m4y<="1110000"whe n 8=>m4y<="1111111"whe n 9=&

59、gt;m4y<="1111011"when others=>m4y<="0000000" end case;end p rocess;end;點(diǎn)陣library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;-lOOOhz clkout3en tity dz isport (clk : in std_logic;lockmode:i n std_logic;dzrow,dzcolr,dzcolg: out std_logic_vector(7 do

60、w nto 0) );end dz;architecture behave of dz issig nal dzcat: in teger range 0 to 7; beginp rocess(clk)beginif(clk'eve nt and clk='1')then if (dzcat=7)the n dzcat<=0;else計(jì)數(shù)器輸出dzcat用于行掃描dzcat<=dzcat+1;end if;end if;end p rocess;pro cess(lockmode,clk)點(diǎn)陣顯示閉鎖圖形beginif(lockmode='1

61、9;)the ncase dzcat iswhe n 0=>dzrow<="01111111"dzcolr<="00000000"dzcolg<="00011000"whe n 1=>dzrow<="10111111"dzcolr<="00000000"dzcolg<="00100100"whe n 2=>dzrow<="11011111"dzcolr<="00000000"dzcolg<="00100100"whe n 3=>dzrow<="11101111"dzcolr<="00000000"dzcolg<="01111110"whe n 4=>dzrow<="11110111"dzcolr<="00000000"dzcolg<="01111110"whe n 5=>dzrow<="11111011"dzcolr<=