組合邏輯電路設(shè)計案例

1、目錄簡單門電路1三態(tài)門及總線緩沖器3轉(zhuǎn)換器6并置運算器8奇偶校驗器9加法器11選擇器12編譯碼器18二輸入與門程序1：出處：4.1.1 例4-1知識點：注意代入語句使用時與實際電路工作情況保持一致，延時是必須要考慮的因素。ENTITY and2 ISPORT (a,b:IN BIT; c:OUT BIT);END ENTITY and2;ARCHITECTURE and2_behav OF and2 ISBEGIN c<=a AND b AFTER 5ns;END ARCHITECTURE and2_behav;程序2：ENTITY and2 ISGENERIC (rise,fall:T

2、IME); PORT (a,b: IN BIT; c: OUT BIT)END ENTITY and2;ARCHITECTURE behav OF and2 ISSIGNAL internal:BIT; BEGIN internal<=a AND b;出處：4.1.4 例4-4知識點：GENERIC語句常用于不同層次之間點的信息傳遞，該例中使用GENERIC語句分別對信號的上升時間和下降時間進行了定義。c<=internal AFTER (rise) WHEN internal='1' ELSE internal AFTER (fall);END ARCHITECT

3、URE behav;程序3：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY nand2 ISPORT (a, b:IN STD_LOGIC; y:OUT STD_LOGIC);END ENTITY nand2;ARCHITECTURE nand2_2 OF nand2 ISBEGIN t1:PROCESS (a, b)IS出處：7.1.1 例7-2知識點：采用RTL方式描述構(gòu)造體，使用CASE語句實現(xiàn)器件的邏輯功能。VARIABLE comb:STD_LOGIC_VECTOR (1 DOWNTO 0); BEGIN comb:=a & b

4、; CASE comb IS WHEN "00"=>y<='1' WHEN "01"=>y<='1' WHEN "10"=>y<='1' WHEN "11"=>y<='0' WHEN OTHERS=>y<='X' END CASE; END PROCESS t1;END ARCHITECTURE nand2_2;三態(tài)門電路程序1：出處：7.1.4 例7-15知識點：利用IF語句

5、的多選擇分支功能描述三態(tài)門，注意輸入、輸出間的控制關(guān)系。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY tri_gate ISPORT (din, en:IN STD_LOGIC; dout:OUT STD_LOGIC);END ENTITY tri_gate;ARCHITECTURE zas OF tri_gate ISBEGINtri_gate1:PROCESS (din, en)IS BEGINIF (en='1') THEN dout<=din; ELSE dout<='Z' END IF; E

6、ND PROCESS;END ARCHITECTURE zas;程序2：出處：7.1.4 例7-16知識點：使用衛(wèi)式BLOCK結(jié)構(gòu)描述，注意條件的設(shè)立。ARCHITECTURE blk OF tri_gate ISBEGINtri_gate2:BLOCK (en='1') BEGIN dout<=GUARDED din;END BLOCK;END ARCHITECTURE blk;八位單向總線緩沖器程序1：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY tri_buf8 ISPORT (din: IN STD_LOGIC_V

7、ECTOR (7 DOWNTO 0) ; dout: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); en:IN STD_LOGIC);END ENTITY tri_buf8;ARCHITECTURE zas OF tri_buf8 ISBEGIN出處：7.1.4 例7-15知識點：采用進程結(jié)構(gòu)，使用IF語句描述器件邏輯功能。tri_buff: PROCESS (en, din)IS BEGIN IF (en='1' ) THEN dout<=din; ELSE dout<="ZZZZZZZZ" END IFEND PROC

8、ESS;END ARCHITECTURE zas;雙向總線緩沖器程序1：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY tri_bigate ISPORT (a, b:INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); en:IN STD_LOGIC; dr:IN STD_LOGIC);END ENTITY tri_bigate;ARCHITECTURE rtl OF tri_bigate出處：7.1.4 例7-23知識點：使用兩個進程語句分別對兩個方向上的數(shù)據(jù)傳輸進行描述。SIGNAL aout, bout:STD_LOG

9、IC_VECTOR (7 DOWNTO 0);BEGINPROCESS (a, dr, en)IS BEGIN IF (en='0') AND (dr='1') THEN bout<=a; ELSE bout<="ZZZZZZZZ" END IF; b<=bout;END PROCESS;PROCESS (b, dr, en)IS BEGIN IF (en='0') AND (dr='0') THEN aout<=b; ELSE aout<="ZZZZZZZZ"

10、 END IF; a<=aout;END PROCESS;END ARCHITECTURE rtl;位矢量/整數(shù)轉(zhuǎn)換器z(i)x_flagq程序1：出處：2.2.3 例2-7知識點：構(gòu)造體采用子程序語句結(jié)構(gòu)的過程語句（PROCEDURE），掌握語句的書寫格式即使用方法。PROCEDURE vector_to_int (z:IN STD_LOGIC_VECTOR; x_f1ag: OUT BOOLEAN; q: INOUT INTEGER) ISBEGIN q:=0; x_f1ag:=FALSE; FOR i IN z'RANGE LOOP q:=q*2;IF(z(i)=1) TH

11、EN q:=q+1; ELSIF(z(i)/=0) THEN x_f1ag:=TRUE; END IF END LOOP; END PROCEDURE vector_to_int;標準邏輯矢量/整數(shù)轉(zhuǎn)換器程序1：出處：3.2.4 例3-1知識點：程序中使用了轉(zhuǎn)換函數(shù)，掌握VHDL語言中常用的轉(zhuǎn)換函數(shù)的使用方法和所在的包集合。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY add5 ISPORT (num:IN STD_LOGIC_VECTOR (2 DOWNTO 0); );END

12、ENTITY add5;ARCHITECTURE rtl OF add5 ISSIGNAL in_num:INTEGER RANGE 0 TO 5; BEGIN in_num<=CONV_INTEGER (num); END ARCHITECTURE rtl;并置運算器程序1：出處：3.3.4 知識點：注意位并置符的使用方法和使用時的注意事項。tmp_b<=b AND (en&en&en&en)；y<=a & tmp_b；八位奇偶校驗電路a(4)a(0)a(1)a(2)a(3)a(5)a(6)a(7)y程序1：LIBRARY IEEE;USE

13、IEEE.STD_LOGIC_1164.ALL;ENTITY parity_check ISPORT(a: IN STD_LOGIC_VECTOR(7 DOWNTO 0); y: OUT STD_LOGIC);END ENTITY parity_check;ARCHITECTURE rtl OF parity_check ISBEGIN PROCESS(a) IS出處：5.1.7 例5-13知識點：注意LOOP語句的書寫格式及使用。VARIABLE tmp: STD_LOGIC; BEGIN tmp:='0' FOR i IN 0 TO 7 LOOP tmp:=tmp XOR

14、a(i); END LOOP; y<=tmp; END PROCESS;END ARCHITECTURE rtl;程序2：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY parity_check ISPORT(a: IN STD_LOGIC_VECTOR(7 DOWNTO 0); y: OUT STD_LOGIC);END ENTITY parity_check;ARCHITECTURE behav OF parity_check ISBEGIN PROCESS(a) ISVARIABLE tmp: STD_LOGIC; BEGIN tmp

15、:= '0' i:=0; WHILE (i<8) LOOP tmp:=tmp XOR a(i); i:=i+1; END LOOP; y<=tmp; END PROCESS;END ARCHITECTURE behav;出處：5.1.7 例5-14知識點：使用帶WHILE條件的LOOP語句描述八位奇偶校驗電路的邏輯功能。加法器程序1：出處：7.1.3 例7-15知識點：采用COMPONENT語句和PORT MAP語句調(diào)用已定義原件半加器half_adder描述全加器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY fu

16、ll_adder ISPORT (a, b, cin:IN STD_LOGIC; s, co:OUT STD_LOGIC);END ENTITY full_adder;ARCHITECTURE full1 OF full_adder ISCOMPONENT half_adder IS PORT (a, b:IN STD_LOGIC;s, co:OUT STD_LOGIC);END COMPONENT;SIGNAL u0_co, u0_s, u1_co:STD_LOGIC;BEGIN u0:half_adder PORT MAP (a, b, u0_s, u0_co); u1:half_adde

17、r PORT MAP (u0_s, cin, s, u1_co); co<=u0_co OR u1_co;END ARCHITECTURE full1;半加器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY half_adder ISPORT (a, b:IN STD_LOGIC;s, co:OUT STD_LOGIC);END ENTITY half_adder;ARCHITECTURE half1 OF half_adder ISSIGNAL c, d:STD_LOGIC;BEGINc<=a OR b;d<=a NAND b;

18、co<=NOT d;s<=c AND d;END ARCHITECTURE half1;二選一選擇器程序1：出處：1.2知識點：理解硬件描述語言能夠比電原理圖更有效的表示硬件電路的特性。ENTITY mux ISGENERIC(m:TIME: =1ns);PORT (d0,d1：IN BIT； sel：IN BIT； q：OUT BIT)；END ENTITY mux； ARCHITECTURE connect OF mux ISBEGIN出處：2.1知識點：作為一個完整的VHDL程序出現(xiàn)，掌握程序框架的結(jié)構(gòu)；實體與構(gòu)造體的書寫格式；各項參數(shù)的含義。PROCESS(d0,d1,se

19、l)ISVARIBLE temp1,temp2,temp3:BIT;BEGINtemp1:=d0 AND sel;temp2:=d1 AND (NOTsel);temp3:=temp1 OR temp2;q<=temp3 AFTER m;END PROCESSEND ARCHITECTURE connect；程序2（與程序1的描述方式一致，但對原件邏輯功能的描述更簡單）：出處：2.1.2 例2-3知識點：構(gòu)造體內(nèi)部語句采用并行處理方式，即介于BEGIN與END之間的語句將會被同時執(zhí)行。ENTITY mux ISPORT (d0,d1：IN BIT； sel：IN BIT； q：OUT B

20、IT)；END ENTITY mux； ARCHITECTURE dataflow OF mux ISBEGINq<=(d0 AND sel)OR(NOT sel AND d1); END ARCHITECTURE dataflow；程序3：ENTITY mux ISPORT(d0，d1，sel: IN BIT; q: OUT BIT);END ENTITY mux;ARCHITECTURE connect OF mux ISSIGNAL tmp1，tmp2，tmp3: BIT;BEGIN cale:BLOCK出處：2.2.1 例2-4知識點：構(gòu)造體采用BLOCK結(jié)構(gòu)，掌握塊語句結(jié)構(gòu)的書

21、寫格式及使用方法。BEGIN tmp1<=d0 AND sel; tmp2<=d1 AND (NOT sel); tmp3<=tmp1 OR tmp2; q<=tmp3; END BLOCK cale;END ARCHITECTURE connect;程序4：出處：2.2.2 例2-6知識點：構(gòu)造體采用進程語句結(jié)構(gòu)，掌握進程（PROCESS）語句結(jié)構(gòu)的書寫格式及使用方法。ENTITY mux ISPORT(d0,d1,sel: IN BIT; q: OUT BIT);END ENTITY mux;ARCHITECTURE connect OF mux IS BEGIN

22、cale: PROCESS(d0,d1,sel) IS VARIABLE tmp1,tmp2,tmp3: BIT; BEGINtmp1:=d0 AND sel; tmp2:=d1 AND (NOT sel); tmp3:=tmp1 OR tmp2; q<=tmp3 ; END PROCESS cale; END ARCHITECTURE connect;程序5：ENTITY mux2 ISPORT (d0,d1,sel:IN BIT; q:OUT BIT);END ENTITY mux2;ARCHITECTURE struct OF mux2 ISCOMPONENT and2 IS PO

23、RT (a,b:IN BIT; c:OUT BIT);END COMPONENT;出處：4.3.1 例4-16知識點：二選一電路采用結(jié)構(gòu)化的方式描述構(gòu)造體，使用了COMPONENT語句和PORT MAP語句，屬于最底層的描述方式，與實際電路最貼近。COMPONENT or2 IS PORT (a,b:IN BIT; c:OUT BIT);END COMPONENT;COMPONENT inv IS PORT (a:IN BIT; c:OUT BIT);END COMPONENT;SIGNAL aa,ab,nsel:BIT;BEGIN u1:inv PORT MAP (sel,nsel);u2:

24、and2 PORT MAP (nsel,d1,ab); u3:and2 PORT MAP (d0,sel,aa); u4:or2 PORT MAP (aa,ab,q);END ARCHITECTURE struct;程序6：出處：5.1.5 例5-7知識點：利用IF語句的二選擇控制功能對二選一電路的邏輯控制進行描述。ARCHITECTURE rtl OF mux2 ISBEGINPROCESS (a, b, sel) ISBEGINIF (sel='1') THENc<=a;ELSEc<=b;END IF;END PROCESS;END ARCHITECTURE r

25、tl;四選一選擇器程序1：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY mux4 IS PORT (i0,i1,i2,i3,a,b:IN STD_LOGIC; q:OUT STD_LOGIC);END ENTITY mux4;ARCHITECTURE behav OF mux4 ISSIGNAL sel:INTEGER;出處：5.2.4 例5-18知識點：注意選擇信號代入語句的使用。條件并行執(zhí)行，不具有優(yōu)先級。出處：4.1.1 例4-2知識點：注意條件代入語句的使用。BEGIN W

26、ITH sel SELECT q<=i0 AFTER 10ns WHEN 0, i1 AFTER 10ns WHEN 1, i2 AFTER 10ns WHEN 2, i3 AFTER 10ns WHEN 3, 'X' AFTER 10ns WHEN OTHERS; sel<=0 WHEN a='0' AND b='0' ELSE 1 WHEN a='1' AND b='0' ELSE 2 WHEN a='0' AND b='1' ELSE3 WHEN a='1&

27、#39; AND b='1' ELSE 4;END ARCHITECTURE behav;程序2：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGEND.ALL;ENTITY mux4 ISPORT (input:IN STD_LOGIC_VECTOR (3 DOWNTO 0); sel:IN STD_LOGIC_VECTOR (1 DOWNTO 0); y:OUT STD_LOGIC);出處：4.2.1 例4-6知識點：采用RTL描述方式描述四選一電路，注意構(gòu)造體的邏輯功能描述的方法，與上例進行

28、比較。END ENTITY mux4;ARCHITECTURE rtl OF mux4 ISBEGINy<=input(0) WHEN sel="00" ELSE input(1) WHEN sel="01" ELSE input(2) WHEN sel="10" ELSE input(3);END ARCHITECTURE rtl;程序3：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux4 ISPORT(input: IN STD_LOGIC_VECTOR (3 DOWNT

29、O 0); sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0); y: OUT STD_LOGIC);END ENTITY mux4;ARCHITECTURE rtl OF mux4 ISBEGIN出處：5.1.5 例5-8知識點：利用IF語句的多選擇控制功能對四選一電路的邏輯功能進行描述；選擇條件順序執(zhí)行，具有優(yōu)先級。注意語句自身為順序語句。PROCESS(input, sel) IS BEGIN IF(sel="00") THEN y<=input(0); ELSIF(sel="01") THEN y<=input

30、(1); ELSIF(sel="10") THEN y<=input(2); ELSE y<=input(3);END IF; END PROCESS;END ARCHITECTURE rtl;程序4：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux4 ISPORT(a,b,i0,i1,i2,i3: IN STD_LOGIC; q: OUT STD_LOGIC);END ENTITY mux4;ARCHITECTURE mux4_behave OF mux4 ISSIGNAL sel: INTEGER RAN

31、GE 0 TO 3;BEGIN出處：5.1.6 例5-9知識點：利用CASE語句的多選擇控制功能對四選一電路的邏輯功能進行描述；選擇條件并行執(zhí)行，不具有優(yōu)先級。注意語句自身為順序語句。B: PROCESS(a,b,i0,i1,i2,i3) IS BEGIN sel<='0' IF(a='1') THEN sel<=sel+1; END IF; IF(b='1') THEN sel<=sel+2; END IF; CASE sel ISWHEN 0=>q<=i0; WHEN 1=>q<=i1; WHEN 2

32、=>q<=i2; WHEN 3=>q<=i3; END CASE; END PROCESS;END ARCHITECTURE mux4_behave;程序5：出處：5.2.3 例5-17知識點：利用條件信號代入語句對四選一電路的邏輯功能進行描述；條件順序執(zhí)行，具有優(yōu)先級。注意語句自身為并發(fā)語句。ENTITY mux4 IS PORT(i0,i1,i2,i3,a, b: IN STD_LOGIC; q: OUT STD_LOGIC);END ENTITY mux4;ARCHITECTURE rtl OF mux4 ISSIGNAL sel: STD_LOGIC_VECTO

33、R(1 DOWNTO 0); BEGIN sel<=b & a;q<=i0 WHEN sel="00" ELSE i1 WHEN sel="01" ELSE i2 WHEN sel="10" ELSE i3 WHEN sel="11" ELSE 'X'END ARCHITECTURE rtl;三-八譯碼器程序1：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY decode_3to8 ISPORT(a,b,c,G1,G2A,G2B:

34、IN STD_LOGIC; y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY decode_3to8;ARCHITECTURE rtl OF decode_3to8 ISSIGNAL indata: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN出處：5.1.6 例5-10知識點：利用CASE語句對譯碼器的邏輯功能進行描述，注意體會語句內(nèi)部的并行執(zhí)行過程與WHEN OTHERS的使用。indata<=c & b & a; PROCESS(indata,G1,G2A,G2B) IS BEGIN IF(G1='1' AND G2A='0' AND G2B='0') THEN CASE indata IS WHEN "000"=>y<="11111110" WHEN "001"=>y<="11111101" WHEN "010"=>y<