AT89C51 電氣專業(yè)外文翻譯

1、the at89c51 is a low-power, high-performance cmos 8-bit microcomputer with 4k bytes of flash programmable and erasable read only memory (perom). the device is manufactured using atmels high-density nonvolatile memory technology and is compatible with the industry-standard mcs-51 instruction set and

2、pinout. the on-chip flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. by combining a versatile 8-bit cpu with flash on a monolithic chip, the atmel at89c51 is a powerful microcomputer which provides a highly-flexible and cost-effective s

3、olution to many embedded control applications. function characteristic the at89c51 provides the following standard features: 4k bytes of flash, 128 bytes of ram, 32 i/o lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and

4、 clock circuitry. in addition, the at89c51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, timer/counters, serial port and interrupt system to continue functioning. the pow

5、er-down mode saves the ram contents but freezes the oscillator disabling all other chip functions until the next hardware reset. pin description vcc：supply voltage. gnd：ground. port 0： port 0 is an 8-bit open-drain bi-directional i/o port. as an output port, each pin can sink eight ttl inputs. when

6、1s are written to port 0 pins, the pins can be used as highimpedance inputs.port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. in this mode p0 has internal pullups.port 0 also receives the code bytes during flash program

7、ming,and outputs the code bytes during programverification. external pullups are required during programverification. port 1 port 1 is an 8-bit bi-directional i/o port with internal pullups.the port 1 output buffers can sink/source four ttl inputs.when 1s are written to port 1 pins they are pulled h

8、igh by the internal pullups and can be used as inputs. as inputs,port 1 pins that are externally being pulled low will source current (iil) because of the internal pullups.port 1 also receives the low-order address bytes during flash programming and verification. port 2 port 2 is an 8-bit bi-directi

9、onal i/o port with internal pullups.the port 2 output buffers can sink/source four ttl inputs.when 1s are written to port 2 pins they are pulled high by the internal pullups and can be used as inputs. as inputs,port 2 pins that are externally being pulled low will source current, because of the inte

10、rnal pullups.port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses. in this application, it uses strong internal pullupswhen emitting 1s. during accesses to external data memory that use 8-bit addres

11、ses, port 2 emits the contents of the p2 special function register.port 2 also receives the high-order address bits and some control signals during flash programming and verification. port 3 port 3 is an 8-bit bi-directional i/o port with internal pullups.the port 3 output buffers can sink/source fo

12、ur ttl inputs.when 1s are written to port 3 pins they are pulled high by the internal pullups and can be used as inputs. as inputs,port 3 pins that are externally being pulled low will source current (iil) because of the pullups.port 3 also serves the functions of various special features of the at8

13、9c51 as listed below: port 3 also receives some control signals for flash programming and verification. rst reset input. a high on this pin for two machine cycles while the oscillator is running resets the device. ale/prog address latch enable output pulse for latching the low byte of the address du

14、ring accesses to external memory. this pin is also the program pulse input (prog) during flash programming.in normal operation ale is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped dur

15、ing each access to external data memory. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only during a movx or movc instruction. otherwise, the pin is weakly pulled high. setting the ale-disable bit has no effect if the microcontroller

16、is in external execution mode. psen program store enable is the read strobe to external program memory.when the at89c51 is executing code from external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory.

17、 ea/vpp external access enable. ea must be strapped to gnd in order to enable the device to fetch code from external program memory locations starting at 0000h up to ffffh. note, however, that if lock bit 1 is programmed, ea will be internally latched on reset.ea should be strapped to vcc for intern

18、al program executions.this pin also receives the 12-volt programming enable voltage(vpp) during flash programming, for parts that require12-volt vpp. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplif

19、ier. oscillator characteristics xtal1 and xtal2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 1.either a quartz crystal or ceramic resonator may be used. to drive the device from an external clock source,

20、 xtal2 should be left unconnected while xtal1 is driven as shown in figure 2.there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specificat

21、ions must be observed. figure 1. oscillator connections figure 2. external clock drive configuration idle mode in idle mode, the cpu puts itself to sleep while all the onchip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the special functions regi

22、sters remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset.it should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the int

23、ernal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle is terminated by reset, the instruction following the one that invokes idle s

24、hould not be one that writes to a port pin or to external memory.power-down mode in the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. the on-chip ram and special function registers retain their values until the power-down mo

25、de is terminated. the only exit from power-down is a hardware reset. reset redefines the sfrs but does not change the on-chip ram. the reset should not be activated before vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabili

26、ze. program memory lock bits on the chip are three lock bits which can be left unprogrammed (u) or can be programmed (p) to obtain the additional features listed in the table below. when lock bit 1 is programmed, the logic level at the ea pin is sampled and latched during reset. if the device is pow

27、ered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. it is necessary that the latched value of ea be in agreement with the current logic level at that pin in order for the device to function properly 該at89c51是一個低功耗，高性能cmos 8位4k的閃存和可擦除可編程只讀存

28、儲器。該設(shè)備是采用atmel的高密度非易失性存儲器技術(shù)，并與兼容行業(yè)標準的mcs - 51指令集和引腳。片上閃存程序存儲器可重新編程的系統(tǒng)或由傳統(tǒng)的非易失性存儲器編程。通過將通用的8位cpu與flash在單片芯片，愛特梅爾at89c51的是一個強大的微型計算機提供了一個高度靈活的和成本有效的解決方案許多嵌入式控制應(yīng)用。 功能特點 該at89c51提供以下標準特性：4k字節(jié)的閃存，128 mb內(nèi)存，32余個字節(jié)/ o線，兩個16位定時器/計數(shù)器，1個向量兩級中斷結(jié)構(gòu)，全雙工串行端口，片內(nèi)振蕩器和時鐘電路。此外，at89c51目的是為降低到零頻率靜態(tài)邏輯，支持兩種軟件可選省電模式?？臻e模式停止的c

29、pu，同時允許的ram，定時器/計數(shù)器，串行端口和中斷系統(tǒng)繼續(xù)運作。掉電模式保存ram的內(nèi)容，但凍結(jié)振蕩器禁用直到下一次硬件復(fù)位所有其他片上功能。 引腳說明 虛擬通道連接：電源電壓。 接地：接地。 端口0： 端口0是一個8位漏極開路雙向i / o端口。作為一個輸出端口，每個引腳可以吸收8 ttl輸入。當(dāng)1秒被寫入端口0引腳，該引腳可作為高電平輸入端。引腳 0也可以配置為低電平地址/在外部程序和數(shù)據(jù)存儲器訪問數(shù)據(jù)總線。在這種模式下p0有內(nèi)部上拉電阻。引腳 0還收到了flash編程的代碼字節(jié)，在programverification和產(chǎn)出的代碼字節(jié)。需要外部上拉過程中programverifica

30、tion。 端口1 端口1是一個8位雙向i / o口與內(nèi)部pullups.the端口1輸出緩沖器可匯/源4 1秒的ttl inputs.when寫入端口1它們拉高，由內(nèi)部上拉電阻，可以引腳作為投入。作為輸入，端口1引腳被外部退出是因為內(nèi)部pullups.port一低的電源電流（iil的）也獲得了閃存編程和核查的低位地址字節(jié)。 端口2 端口2是一個8位雙向i / o口與內(nèi)部pullups.the端口2輸出緩沖器可匯/源4 1秒的ttl inputs.when寫入端口2它們拉高，由內(nèi)部上拉電阻，可以引腳作為投入。為輸入，端口2個引腳被外部拉低的來源目前由于內(nèi)部pullups.port，2發(fā)出的高位

31、地址字節(jié)中提取從外部程序存儲器以及在外部數(shù)據(jù)存儲器訪問，使用16位地址。在此應(yīng)用程序，它使用的內(nèi)部pullupswhen發(fā)射1秒。在訪問外部數(shù)據(jù)存儲器，使用8位地址，端口2排放的p2的特殊功能register.port 2的內(nèi)容訪問也收到了高地址位并在閃存編程和驗證了一些控制信號。 端口3 端口3是一個8位雙向i / o的內(nèi)部pullups.the端口3輸出緩沖器可吸收/源端口4 1秒的ttl inputs.when寫入端口3它們拉高，由內(nèi)部上拉電阻，可以引腳作為投入。作為投入，港3個管腳被外部拉因為pullups.port三低的電源電流（iil的），還擔(dān)任了下面列出at89c51的各種特殊功能的功能： 端口3還收到閃存編程和驗證了一些控制信號。 rst 復(fù)位輸入。關(guān)于這兩個機器周期針高，而振蕩器運行重置設(shè)備。 啤酒/ prog 聯(lián)系地址鎖存期間的外部存儲器訪問的地址低字節(jié)鎖存使能輸出脈沖。該引腳也脈沖輸入的程序在正常運行閃存programming.in啤酒（prog）被發(fā)射在恒定速率的1 / 6振蕩器的頻率，并且可以是外部定時或時鐘的用途。但是，請注意，一個ale脈沖被跳過每次到外部數(shù)據(jù)存儲器訪問。 如果需要，啤酒操作可以通過設(shè)置位sfr的位置8eh 0。隨著位設(shè)置，ale為活躍只在一執(zhí)行movx或movc指令。否則，腳弱拉高。設(shè)置啤酒，禁用位沒有任何效果，