大連交通大學coa考試題2

1、I. Suppose both instructions and data are 16bits long, the opcode field in 4 bits long, there is a program fragment( 程序段 ) with three instructions stored from memory location 300 to 302 and two data items stored in memory location 941 and 942, all the number arehexadecimal(十六進制數(shù) ) in the figure. （ 1

2、6 points）(Notes: Load x means Load AC from memory location x;Store x means Store AC to memory location x;Add （ x） means Operand pointed by the content of location X is added to AC)Answer the following questions:(Put the answer on the next page)(1) Give the PC value before and after the program fragm

3、ent execution.( 2 points )(2) Tell the final result of memory location 941. ( 2 points )(3) Tell the addressing mode and addressing range of the instruction stored in memory location 300 and 301.( 6 points )(4) Write out the all the micro-operation of the instructions stored in memory location 301 .

4、( 6 points )。300Load941301Add(500)302Store941。500942。94109419420942Answer: 1. before：（PC）=_300_(1 points)After: （PC）=_303_(1 points)2.Final result of memory location 941: (941)=_1283_(2 points)3.instruction stored in memory location 300:Addressing mode:_ _direct_(1 points)12Addressing range: _2 =4K

5、_(2 points)instruction stored in memory location 301:Addressing mode: _indirect _(1 points)16Addressing range:_ 2 =64K _(2 points)4. Write out the micro-operation of the instructions stored in memory location 301.Add (500);Fetch cycleIndirect cycleExecute cyclet1: (PC) -> MARt1: Ad(MBR) -> MAR

6、t1: (MBR) -> MARt2: (MAR) -> Memoryt2:(MAR) -> Memoryt2: (MAR) -> Memoryread -> Memoryread ->Memoryread ->Memoryt3: Memory -> MBRt3:Memory-> MBRt3: Memory-> MBRt4: (MBR) -> IRt4:(MBR)+(AC)-> AC(PC) +1 -> PC(2 points)(2 points)(2 points)II. A set associative cac

7、he consists of 32k lines, divided into 8-line sets. Main memory contains 16M blocks of 256 words each. Answer the following questions: ( 16 points)(1) Show the format of the main memory address. ( 7 points)(2)For a certain block of main memory, how many cache lines can it map to? ( 2 points)(3) For

8、a certain line of cache memory, how many blocks of main memory may be mapped to ? ( 2 points)(4) Where in the cache is the word from memory location ABCDE8F8 mapped? ( 5 points)Answer:(1) 1) Line size=Block size=256words=2 8words => Word# =8bits ( 1 points)2) Number of sets=32klines/ 8lines/set =

9、2 12sets =>Set# =12bits ( 2 points)3)Memory size =16M x 256words=2 32words => Length ofRA =32 bits=> Tag=32-12-8=12bits ( 2 points)so, address format is : (2 points)tagset#word#12-bit12-bit8-bit(2)8 lines ( 2 points)(3)2 Tag=212=4K blocks (2 points)(4)ABCDE8F8H=1010， 1011， 1100， 1101， 1110，

10、 1000， 1111， 1000 ( 2 points)Tag=ABCHSET#=DE8Hmemory location ABCDE8F8 can be mapped to any line of set DE8H, tag=( 2 points)ABCH ( 1 points)III. Suppose the Hamming code 0101 1101 0101 is just read from memory , please use the Hamming algorithm to determine what is thevalid 8-bit data? (14 points)k

11、(1) 2 -1 m+k m=8 => k=4-bit (1 points)(2) Set up a table (3 points)Bit PositionPosition numberCheck bitData bit0121100D8111011D71101010D6091001D5181000C8170111D4160110D3050101CD21401000300114D1120010C2010001C11C8C 4C2C 1 =1001 (1 points)D8 D 7 D6 D 5 D4 D3 D 2 D1=01011011(1 points)(3)Calculates n

12、ew check bits:C1 (1,2,4,5,7)= 1 1 1 1=1(1 points)C2 (1,3,4,6,7)= 0 1 0 1=1(1 points)C4 (2,3,4,8) 1= 0 1 0=0(1 points)C8 (5,6,7,8) 1= 0 1 0= 0 (1 points)=> new check bits： C 8C 4C 2C 1=0011（ 4） syndrome words=C 8C4C 2C1 C 8C 4C 2C 1=1001 0011=1010 (2 points)D6 has an error, so correct D6=1 (1 poin

13、ts) So correct data bit :0111 1011 (1 points)IV . In multi-processor systems, MESI protocol is used to solve the problem of cache coherence. According to the given figure, answer the following questions:InitialSnoopy1)(14 points)This is the case of _.2) Please complete this figure.3) With this case

14、, please fill best answers into the following table.The states in beginWhere is theThe states in endInitialsnoopyValid data?ActionssnoopyInitial1) This is the case of_write hit _.2) Please complete this figure.3) With this case , please fill best answers into the following table.The states in beginW

15、here is theActionsThe states in endInitialsnoopyValid data?InitialsnoopyEIThe cache inThe initialjust updates the word,MIExclusiveand transitions to modified state.stateandMM.SSThe cache inThe initialsignals itsexclusiveMIsharedstateownership of the cache line on theand MMbus, the snoopy in shared s

16、tatetransitionsto invalidstate. Theinitial updates the word andtransitions to modified state ,MIOnlytheThe initialupdates the word andMIcacheinstill in modified state.modifiedstateV . True or false ( true:,false:× )（） 1.TheFIFOcharacteristics of stack makes it capable of helpingimplementing nes

17、ted procedure call and nested interrupt handling.() 2. More than one module may control bus at one time.() 3. The operation code must not be included in an instruction.() 4. Address bus width is 32 bits, so addressing range is 4M.() 5.For RAID 5,parity stripes across all disks, round robin allocatio

18、n forparity stripe, avoids RAID 4 bottleneck at parity disk.() 6. Index addressing mode is good for accessing arrays.() 7. In a multiple platters hard disk system, aligned tracks on each platter formcylinder.) 8. In computer , address information can be viewed as unsigned integer.) 9. The worst fact

19、or to affect instruction pipeline effectiveness is branch instruction .) 10. Cache mechanism bases on the fact that during the course of the execution of aprogram, memory references tend to cluster, this refers to as locality of reference.II. True or false ( true:,false:×)（ × ） 1.TheFIFOch

20、aracteristics of stack makes it capable of helpingimplementing nested procedure call and nested interrupt handling.(×) 2. More than one module may control bus at one time.(×) 3. The operation code must not be included in an instruction.(×) 4. Address bus width is 32 bits, so addressin

21、g range is 4M.( ) 5.For RAID 5,parity stripes across all disks, round robin allocation forparity stripe, avoids RAID 4 bottleneck at parity disk.() 6. Index addressing mode is good for accessing arrays.() 7. In a multiple platters hard disk system, aligned tracks on each platter formcylinder.() 8. I

22、n computer , address information can be viewed as unsigned integer.(×)9. Theworst factorto affectinstructionpipelineeffectiveness is branchinstruction .() 10. Cache mechanism bases on the fact that during the course of the execution ofa program,memory references tend to cluster, this refers to

23、as locality ofreference.1.Control unit uses some input signals to produce control signals that open the gates ofinformation paths and let the micro-operations implement.Which is NOT the output signals of control unit? _A. subtraction control signal to ALUB. clock and flagsC. control signals to the I

24、/O modulesD. memory read and write2.An 8-bit twos complement data 10011001 is extended to a 16-bit data that equals to_A. 1000 0000 0001 1001B. 0000 0000 1001 1001C. 1111 1111 1001 1001D. 1111 1111 0110 01113.The _ register is useed to point to the top of stackA. PCB. SPC.MARD.MBR4.The range of an 8

25、-bit two s complement representation is between _.A. -127 to +127B. -128to127C. 0 to 255D. -128to1285. Which of the following types fo memory si erasable semiconductor memory?_A. DVD-RWB. Hard diskC. cacheD. maskROM6. The correct sequences of interrupt precess stems are _A. suspending, branching,pro

26、cessing & resumingB. branching, suspending,processing & resumingC. suspending, resuming, branching & processingD. processing, branching,resuming & suspending7. With mapping function of cache ,any block of main memory can be mapped to any line of cache, it is _.A. Associative MappingB

27、. direct MappingC. Set Associative MappingD. Random Mapping8. Which of the following integer(n=8,represented in twos complement) will not cause overflow after arithmetic shift left one bit operation?_A. 00110111B.01000000C.10110111D.011110119. The difference between tightly coupled system and loosel

28、y coupled system is _?A. tightly coupled execute a single instruction,loosely coupled executes different instructionB. tightly coupled has shared memory ,loosely coupled has distributed memoryC. tightly coupled operates on a single data set,loosely coupled operates on different datasetD. tightly cou

29、pled has single CPU ,loosely coupled has a set of CPU10. Comparing withprogrammed I/O,interrupt-driver I/O further raises the usage rate ofCPU operations,because_.A.it isn tnecessary for CPU to save &restore sceneB.it isn tnecessary for CPU to intervens the data transferC.both A and BD. it isn t

30、 necessary for CPU to read & check status repeatedly11. In DMA,the DMA module takes over the operations of data transferring from CPU,it means_.A.the DMA module can fetch and execute instructions like CPU doesB. the DMA module can hold the bus to transfer data to or from memory using stealing cy

31、cle techniqueC.the DMA module and CPU work together(co-operate) to transfer data into or from memoryD.when DMA module gets ready,it issueinterrupt request signal to CPU for getting interrupt service12. Which of the following statement about DMA is NOT TRUE? _A. When large volumes of data are to be m

32、oved between memory and high speed device DMA is a more efficient technique.B. The processor is involved only at the beginning and the end of the transferC. When the transfer is complete,the DMA module sends an interrupt signal to the processorD. The CPU will finish the present instruction and respo

33、nd to the DMA request.13. Twos complement multiplication algorithm was developed by_A.Gorden mooreB. Von NeumannC. Booth coupleD.Bill gates14. Suppose a floating number +1.1010001*2(+10100) ,choose the correct result based on the following format:Sign bit(1 bit)Biased exponent(8bit)Twos complement S

34、ignificand(23bit)15. Which of the following statement s about DRAM is not trueA. Bit stored as charge in capacitorsB. Need refreshing even when poweredC. simpler construction and smaller per bit than SRAMD. Usuallyused as cache memory16. The advantage of direct mapping technique is_,its main disadva

35、ntage is thatitmay cause _.A. simple and inexpensive to implement ,a phenomemon known as thrashingB. there is flexibility of block repacement,the complex circuitry required to examine the tags of all cache lines in parallelC. simple and inexpensive to implement,the complex circuitry required to exam

36、ine thetages of all cache lines in parallelD. there is flexibility of block replacement, a phenomenon known as thrashing.17. For a k-way set associative mapping,the cache is divided into v set, each of which consists of k lines,the cache total line number is m, in the extreme case of v=m,k=l,the set

37、 associative technique reduces to _,and for v=1 k= m, it reduce to_.A. associative mapping,direct mappingB. random mapping,direct mappingC. direct mapping,radom mappingD. direct mapping,associative mapping18. Which of the following statements about hard disk is false?A . For hard disk,minimum block

38、size is one sectorB. The aim of formatting disk is to add additional information to mark tracks and sectors which is available to user.C. Data is striped by cylinderD. Hard disk seek time is the time for the head to move to the correct track.19. _ isnt registerA. PCB. ACC.MARD.ALU20. Before micro-op

39、eration Write ->memory or Read->memory, the address the memory location must be put in _A. MARB.MBRC.PCD.AC21.The ID field of a typical hard disk is_.A. synch byte ,track# ,sector#, head#,CRCB. synch byte,cylinder#head#,sector#, CRCC. synch byte,sector#, side#, track#, CRCD. synch byte,sector # ,track#,head#,crc22. Which is not a feature of CISC processor,A. complex an flexible addressingB. abundant instruction setC.simple format an fixed instruction lengthD. strong support to high language23. If the speed of main memory is as fast as CCPU, which technique i