數(shù)字設計 第八章 時序邏輯設計實踐 (3)學習課件

Chapter8sequentiallogicdesignpractices本章重點：計數(shù)器：含觸發(fā)器構成的計數(shù)器及MSI組件計數(shù)器，序列發(fā)生電路移位寄存器：作為數(shù)據(jù)移位的基本功能，和構成環(huán)形計數(shù)器、扭環(huán)計數(shù)器，序列發(fā)生電路，檢測電路2/28/20258.1documentationstandardsInlogicblock,inputisontheright,outputisontheleft.inputoutput………………PRCLR……Edge-triggered……CCLKPulse-triggered2/28/2025chapter88.2latchesandflip-flops1.SSIlatchesandflip-flops74×74—dualDf-fs74×109—dualJ-K’f-fs74×375—quadDlatch2.Switchdebouncing

消除機械開關在開、關時產(chǎn)生的觸點機械抖動3.Bus-holder

避免三態(tài)輸出總線上長期無信號而由噪聲、干擾等產(chǎn)生較大電流而損壞器件的問題。2/28/2025chapter8Switchdebouncing常用的按鍵、開關RS觸發(fā)器為常用的硬件去抖。當機械觸點斷開、閉合時,電壓信號如下圖。抖動時間的長短由按鍵的機械特性決定,一般為5ms～10ms。2/28/2025chapter83.MultibitregistersandlatchesCollectionoftwoormoreDf-fswithacommonclockinput.Cabbeusedtostoredata.2/28/2025chapter88.4countersAnysequentialcircuitwhosestatediagramisasinglecycle.stores(andsometimesdisplays)thenumberoftimesaparticulareventorprocesshasoccurred,ofteninrelationshiptoaclocksignal.Modulus—thenumberofstatesinthecycleS1SjSmS3S2……Modulo-mcounterclock2/28/2025chapter8GeneraltypesofelectroniccountersIncountingsequenceupcounters,whichincrease(increment)invaluedowncounters,whichdecrease(decrement)invalueUp–downcounter–countsbothupanddown,undercommandofacontrolinputIncountercircuitAsynchronous(ripple)counterSynchronouscounterRingcounterJohnsoncounter2/28/2025chapter81、ripplecounters4-bit：CountingtimingdiagramQ0Q1Q2Q3Counteroutput（LSB）（MSB）CLKQ1Q0Q3Q2CLKCLKQQTCLKQQTCLKQQTCLKQQT11112/28/2025chapter84-bitcounter’sfunctionaltableQ3Q2Q1Q0Q3*Q2*Q1*Q0*0000000100010010001000110011010001000101010101100110011101111000Q3Q2Q1Q0Q3*Q2*Q1*Q0*10001001100110101010101110111100110011011101111011101111111100002/28/2025chapter8Issue1：howtomakeadowncounterbyTf-fs？Issue2：howtomaketheripplecounterbyusingDandJ-Kf-fs？Digitalfrequencydivider(divided-by-2n)divide-by-2CLKQ1Q0Q3Q2divide-by-4divide-by-8divide-by-162/28/2025chapter82、SynchronouscountersAllflip-flopschangetheirstatesatthesametriggeringtimeofacommonCLKsignal.Workingfeatures：

CNTENsignalpropagatesserially.transitionequations：

Q0*=EN0·Q0’+EN0’·Q0

Q1*=EN1·Q1’+EN1’·Q1

Q2*=EN2·Q2’+EN2’·Q2

Q3*=EN3·Q3’+EN3’·Q3EN0EN1EN2EN3(LSB)(MSB)synchronousserialcounter2/28/2025chapter8(LSB)(MSB)EN0EN1EN2EN3CNTENsignalcontrolsthef-fssimultaneously;thefastestbinarycounterstructure.判斷該計數(shù)器是升序的或降序的？寫出完整的轉移方程、功能表和時序圖。作為作業(yè)synchronousparallelcounter2/28/2025chapter8binarysynchronouscounterdesignwithDflip-flopsExp1:designa3-bitbinarysynchronousdowncounter,counteroutputQ2(msb),Q1,Q0。thefunctionaltable：Q2Q1Q0Q2*Q1*Q0*0001110010000100010110101000111011001101011111102/28/2025chapter8excitationtableofthecounterQ2Q1Q0Q2*Q1*Q0*D2D1D0J2K2J1K1J0K00001111111d1d1d0010000000d0dd10100010010dd11d0110100100dd0d1100011011d11d1d101100100d00dd1110101101d0d11d111110110d0d0d1excitationequations：D2=Q2Q1+Q2Q0+Q2’Q1’Q0’D1=Q1Q0+Q1’Q0’D0=Q0’……2/28/2025chapter8designsynchronouscounterwithmodulelessthan2nmoduleofthecounterm<2n，thedispositionofunusedstate：minimalriskminimalcost，needtoverifytheunusedstatethatassuresthecircuitcanbereturnedtothenormalExp2：designamodulo-5counter，itcounttheclockticksfrom000to100，synthesisbyDflip-flopinminimalcost.2/28/2025chapter83、MSIcountersandapplicationssynchronous4-bitbinarycounter74×163clearloadingENT=ENP=CLR_L=LD_L=1，countingRCO（ripplecarryoutput）:whenQDQCQBQA=1111，andENT=1，RCO=1。hold2/28/2025chapter8workinginfree-runningmode(modulo-16counter)MSBLSB74×163isfullysynchronous,itsoutputschangeonlyontherisingedgeofclock.2/28/2025chapter8using74×163inm<16modecounterExp：modulo-11counter

method1：feedback-clearmode(反饋清零)—countthefirstmbinarynumberfrom0000.key：whencountingtothenumberm(m-1),thecounterreturnto0000.so,needafeedbackcircuitF，andwhenQDQCQBQA=1010,makeCLR_Lasserted.Q0Q1Q2Q3FCLR_L74×163QAQBQCQDCLR2/28/2025chapter8Q3Q2Q1Q0CLR_L0000100011001010011101001010110110101111100011001110100CLR_L=(Q3·Q1)’Q0Q1Q2Q3FCLR_L74×163QAQBQCQDCLR2/28/2025chapter8verifytheunusedstateUnusedstates1011~1111:

10110000110011011110111100010010011010101000………Itcanrunautomatically.CLR_L=(Q3·Q1)’2/28/2025chapter8using74×163inm<16modecounterMethod2：feedback-loadmode(反饋置數(shù))—countthelastmstatesorarbitrarymcontinualstatesbetween0000and1111.key：makeLD_Lassertedwhencountingtotheendingstate,andtheinitialstateisloaded.①iftheendingstateis1111，usetheRCOoutputtoreloadtheinitialstate.Initialstate=endingstate–countingmodulo+1=15-11+1=5Soallthecountingstateis0101~1111.2/28/2025chapter8referencecircuitoffeedback-load2/28/2025chapter8②iftheendingstateisn’t1111,needacombinationalfeedbackcircuittoreloadtheinitialstate.

initialstate=endingstate–modulo+1or,endingstate=initialstate+modulo-1like，knowingtheendingstateis13，sotheinitialstate=13-11+1=3or,knowingtheinitialstateis2，sotheendingstate=2+11-1=12circuitdesign：besimilartofeedback-clearmode，noteditsoutputneedtobeconnectedtothe

LD_Lof74×163.2/28/2025chapter8referencecircuitoffeedback-loadcountingfrom3to13(0011~1101)2/28/2025chapter874×163cascadingapplicationifthecountingmodulo>16，multiple74×163couldbecascaded.key：countnestingn74×163→maximummodulo16n。connectinglowergradecounter’sRCOoutputtonexthighergradecounter’sENsignal.2/28/2025chapter8Modulo-256free-runcounter2/28/2025chapter816<modulo<256countersExp，amodulo-125countermethods：

feedback-clear—0~124；

feedback-reload—131~255，orarbitrarytwonumberswhosedifferenceis124between0and255.2/28/2025chapter8Othercounters74×161，asynchronousclear4-bitbinarycounter.

asynchronousclear：ifCLR_L=0，QDQCQBQAoutput0000immediately.otherfunctionisasthesameas74×163.use74×161tomodulo-11infeedback-clearmode，countending=1011，CountingNQ3Q2Q1Q0000001000120010300114010050101601107011181000910011010101110112/28/2025chapter8Othercountersdecadescounter74×160（asynchronousclear）74×162(fullysynchronous)74×1694-btup/downcounter2/28/2025chapter8FromcountertotimerncounterclockT=1sModulo-60BCD-7segmentdecoderdisplayer555多諧振蕩器或與非門構成的雙穩(wěn)電路74×16274LS48或74LS49共陰型LED仿真作業(yè)，3人一組，用multisim10或proteus7.0仿真均可，提交仿真程序。2/28/2025chapter84、decodingbinary-counterstates以計數(shù)器的計數(shù)輸出作為譯碼器的輸入，可在譯碼器的輸出端得到周期為8倍計數(shù)時鐘的1：8的脈沖。也稱為8路順序脈沖發(fā)生電路2/28/2025chapter874×163iscombinedwith74×151toobtainasequence-generator.Exp：a“01100101”sequence-generator計數(shù)器+數(shù)據(jù)選擇器法構成的序列發(fā)生器的工作特點:只要計數(shù)器是有效的，在時鐘的觸發(fā)下，循環(huán)地輸出序列。2/28/2025chapter8supplement：buildingsequence-generatorwithDF-Fs設計方法：順序計數(shù)+組合電路例：試設計一個密碼產(chǎn)生器，能依次輸出011010。用順序計數(shù)器的每個計數(shù)值產(chǎn)生一個碼位。000

0001

1010

1011

0100

1101

0Q2Q1Q0Q2*Q1*Q0*SEQ000001000101010100111011100010010111010000110dddd111dddd2/28/2025chapter8circuitforsequence-generatorincountermodeU1A74LS74D1D21Q51Q61CLR11CLK31PR4U1B74LS74D1D21Q51Q61CLR11CLK31PR4U2A74LS74D1D21Q51Q61CLR11CLK31PR4U3A74LS00DU3B74LS00DU3C74LS00DU4A74LS10DU3D74LS00DU5A74LS00DU6A74LS32DD2D1D0Q2Q2'Q1Q1'Q0Q0'SEQ2/28/2025chapter8課堂練習（1）設計一個序列信號檢測器，當電路的輸入端X收到連續(xù)的“1011”時，輸出F為1，并且狀態(tài)可以重疊。狀態(tài)賦值采用QmQm-1…，按gray碼序。（2）設計一個5進制加/減計數(shù)器，當控制信號C=0，計數(shù)器按加1計數(shù)，當C=1，計數(shù)器按減1計數(shù)。用D觸發(fā)器綜合。2/28/2025chapter88.5ShiftRegisterAnn-bitregisterwithaprovisionforshiftingitsstoreddatabyonebitpositionatezchtickoftheclock.Classifybystructure：serial-in,serial-outserial-in,parallel-outparallel-in,serial-outparallel-in,parallel-outShift-rightClassifybyshiftingdirection：Shift-left2/28/2025chapter8Ann-bitnumberDn-1Dn-2……D1D0isstoredinann-bitshiftregister.Shiftleft：shiftfromLSBtoMSBShiftright：shiftfromMSBtoLSBDnewDn-1Dn-2……D1D0D1……Dn-2Dn-1Qn-1Qn-2Q1Q0…D0D1……Dn-2DnewQn-1Qn-2Q1Q0shiftleftshiftright2/28/2025chapter81、shift-registerstructure（1）、serial-in,serial-outAfternclockticks,aninputbitappearsattheserialoutput.itcanbeusedasapulse-postponedcircuit.inputoutputnclocktickt0tn2/28/2025chapter8（2）、serial-in,parallel-out并出serialinparalleloutserial-parallelconversion2/28/2025chapter8（3）、parallel-in,serial-outserialout數(shù)據(jù)并入U1U2D2

Q1

load/shift=1，loaddata，Di=iDload/shift=0，datashift，Di=Qi-11Dn

D10012/28/2025chapter8（4）、parallel-in,parallel-out2/28/2025chapter82、MSIshiftregister74×164,serial-in,parallel-outwithasynchronousclearinput（CLR_L）.shiftdirectionSERA·SERBRXDTXDMCUU174HC164QA3QB4QC5QD6A1B2CLR9CLK8QE10QF11QG12QH132/28/2025chapter8MSIshiftregister74×194，4-bitbidirectional,parallel-in,parallel-outFunctioninputNextstatefunctionS1S0QA*QB*QC*QD*00QAQBQCQDHold01RINQAQBQCShiftright10QBQCQDLINShiftleft11ABCDload注意：此處的左移（QD到QA）、右移（QA到QD）是針對該器件定義的，與數(shù)據(jù)單元的左/右移不同。74×299，8位雙向并入并出型，（通用型）2/28/2025chapter83、applicationofshiftregister:serial/parallelconversioncontrolcircuitparallel-serialconversionparallel-indataparallel-serialconversioncontrolcircuitparallel-outdatasourcedestinationserialdataclocksignalsynchronoussignal2/28/2025chapter8數(shù)字式程控交換機的時分多路復用系統(tǒng)。2/28/2025chapter82/28/2025chapter85、shift-registercountersbedifferfromthebinaryupordowncounters.ringcounterann-bitshiftregistercanbeusedtoobtainacounterwithnstates.4-bitringcounterQ0*=D0=Q3Q1*=D1=Q0Q2*=D2=Q1Q3*=D3=Q22/28/2025chapter8ringcounterinitialstate：Q3Q2Q1Q0=0001D0D1D2D3Q3Q2Q1Q0Q3*Q2*Q1*Q0*00010010001001000100100010000001（D1）Q0（D2）Q1（D3）Q2（D0）Q32/28/2025chapter8StatediagramofringcounterAsinglecircleincluding4statescouldbeusedasamodulo-4counter.(byusing4F-Fs)(是順序脈沖發(fā)生器的一種)0001001001001000normalcycleNotself-correcting0011011011001001011111101101101101011010000011112/28/2025chapter8useMSIshiftregistertoobtainaringcounterRESET=1，loadABCD=0001；

RESET=0，shiftleft其結構一般都是Di接前一級的Qi-1，最后Qn反饋回D0端。2/28/2025chapter8Self-correctingringcounterChangethefeedbackcircuitconnectedtoD0.將環(huán)形計數(shù)器的低三位經(jīng)或非門連到LIN端構成校正電路，即LIN=Q2’Q1’Q0’。So,itisaself-correctingringcounter.2/28/2025chapter8Iftheringcounteradoptactive-low1-out-of-ncode,thentheself-correctingcircuitisa3-inputNANDgatewhichhasQ0~Q3input.11101101101101112/28/2025chapter87、JohnsonCounters(twisted-ringcounter）stucture電路特點：Q3’——D0Q0*=D0=Q3’Q1*=D1=Q0Q2*=D2=Q1Q3*=D3=Q2D0DCLKQQCLRPRDCLKQQCLRPRDCLKQQCLRPRDCLKQQCLRPRQ0Q1Q2Q3CLK2/28/2025chapter8StatediagramofnormalcycleSetinitialQ3Q2Q1Q0=0000，Ann-bitJohnsoncounterhas2nstate.Itcouldbeusedasamodulo-8counter.Q3Q2Q1Q0000000011100100000110111111011112/28/2025chapter8TimingdiagramEachQioutputapulsewhichhas8timesoftheclockperiodand50%dutycycle.也可作為順序脈沖發(fā)生器2/28/2025chapter8用MSI構成扭環(huán)計數(shù)器

RESET_L=0，clear

RESET_L=1，soS1S0=10maketheshiftregistershiftleft，Q3Q2Q1Q0：0000—0001—0011—……—1000。

2/28/2025chapter8JohnsoncounterstatedecoderstateQ3Q2Q1Q0decordingS10000Q3’·Q0’S20001Q1’·Q0S30011Q2’·Q1S40111Q3’·Q2S51111Q3·Q0S61110Q1·Q0’S71100Q2·Q1’S81000Q3·Q2’Eachstatecanbedecodedwitha2-inputANDorNANDgate.Theoutputareglitchfree.JohnsoncounterCLKdecoderQ3Q2Q1Q0Y0Y1Y2Y3Y4Y5Y6Y72/28/2025chapter8Q3Q2Q1Q0Y7Y6Y5Y4Y3Y2Y1Y0decording000001Q3’·Q0’00011Q1’·Q000111Q2’·Q101111Q3’·Q211111Q3·Q011101Q1·Q0’11001Q2·Q1’100010Q3·Q2’2/28/2025chapter8Self-correctingofJohnsoncounterTheother8unusedstateisabnormalcycle.Neithernormalcyclenorabnormalcycleisself-correcting.01011011100100100110110101001010Q3Q2Q1Q02/28/2025chapter8具有自啟動能力的Johnson計數(shù)器：反饋置數(shù)方式校正過程：當前狀態(tài)Q3Q2Q1Q0為0××0時，令計數(shù)器重新裝載計數(shù)初值，下一狀態(tài)到0001。00000001110010000011011111101111010110111001001001101101010010102/28/2025chapter8具有自啟動能力的Johnson計數(shù)器：反饋置數(shù)方式校正過程：當前狀態(tài)Q3Q2Q1Q0為0××0時，U1的輸出LOAD=1，令S1S0=10，74×194重新裝載數(shù)據(jù)，下一狀態(tài)到0001。00000001110010000011011111101111010110111001001001101101010010102/28/2025chapter8移位寄存器在序列檢測和序列發(fā)生中的應用例1、設計一個序列檢測器，當串行輸入X為1010時，輸出F為1，用移位寄存器實現(xiàn)。數(shù)據(jù)左移1100檢測電路2/28/2025chapter8移位寄存器在序列檢測和序列發(fā)生中的應用例1、設計一個序列檢測器，當串行輸入X為1010時，輸出F為1，用移位寄存器實現(xiàn)。數(shù)據(jù)右移檢測電路11002/28/2025chapter8序列發(fā)生器移位寄存器式計數(shù)器作為序列發(fā)生電路的一般結構：序列輸出F下一位產(chǎn)生電路D0QD1QD2QD3Q序列的長度即為電路的狀態(tài)個數(shù)，按狀態(tài)個數(shù)S確定觸發(fā)器（狀態(tài)變量）個數(shù)N，以連續(xù)的N位bit為一個狀態(tài)，在所需生成的序列中按照依次移動1bit的順序找出S個獨立的狀態(tài)。2/28/2025chapter8例2：某序列信號發(fā)生器輸出信號為…011010011010…。試用D觸發(fā)器設計該電路。找狀態(tài)……011010011010……Q2Q1Q0Q2*Q1*Q0*D0(F)011110011010111010100010100010000110010111000dddd111ddddD2=Q1D1=Q0D0=Q2·Q0’+Q2’·Q1’2/28/2025chapter8電路自啟動檢查：Q2Q1Q0=000，Q2*Q1*Q0*=001Q2Q1Q0=111，Q2*Q1*Q0*=110能返回有效狀態(tài)2/28/2025chapter8例3、用移位寄存器產(chǎn)生序列1001101011分析：序列長度10位，設置10個狀態(tài)，左移方式，用每個狀態(tài)產(chǎn)生下一個將要移入的位Q3Q2Q1Q0Q3*Q2*Q1*Q0*D01001001110011011000110110111101101001010010110101101111011011110111111001110110001100100112/28/2025chapter88、lin