數(shù)字系統(tǒng)設(shè)計(jì) - 微處理器設(shè)計(jì)

1Spring2017ZDMC–Lec.#12數(shù)字系統(tǒng)設(shè)計(jì)

DigitalSystemDesign-----微處理器設(shè)計(jì)12講義第十章微處理器設(shè)計(jì)3以微處理器為中心的數(shù)字系統(tǒng)RobotsSupercomputersAutomobilesLaptopsSet-topboxesServersSensorNetsRoutersSmartphonesMediaPlayersGamesCameras10.1微處理器結(jié)構(gòu)什么是微處理器？微處理器由一片或少數(shù)幾片大規(guī)模集成電路組成的中央處理器。這些電路執(zhí)行控制部件和算術(shù)邏輯部件的功能。微處理器能完成取指令、執(zhí)行指令，以及與外界存儲(chǔ)器和邏輯部件交換信息等操作，是微型計(jì)算機(jī)的運(yùn)算控制部分。微處理器的主要結(jié)構(gòu)馮諾依曼結(jié)構(gòu)將程序存儲(chǔ)和數(shù)據(jù)存儲(chǔ)放在同一物理存儲(chǔ)空間相同的總線硬件簡(jiǎn)單哈佛結(jié)構(gòu)將程序存儲(chǔ)和數(shù)據(jù)存儲(chǔ)分別放在不同的物理存儲(chǔ)空間不同的總線靈活、速度快4馮諾依曼計(jì)算機(jī)模型四個(gè)主要組成部分輸入、輸出、存儲(chǔ)器微處理器5馮諾依曼計(jì)算機(jī)模型微處理器內(nèi)部結(jié)構(gòu)微處理器的兩個(gè)主要部分：控制單元用于控制數(shù)據(jù)通路的所有操作，實(shí)現(xiàn)微處理器運(yùn)算的正確性數(shù)據(jù)通路主要包括運(yùn)算單元ALU、存儲(chǔ)單元（寄存器）及其相互連接6微處理器內(nèi)部結(jié)構(gòu)指令集專(zhuān)門(mén)執(zhí)行一些指令集的微處理器利用指令集編寫(xiě)不同的程序完成不同的處理任務(wù)7微處理器整體結(jié)構(gòu)需要多少條指令集？每條指令是什么？每條指令的操作碼（opcode）是什么？指令編碼使用多少位寬的數(shù)據(jù)？程序指針（ProgramCounter,PC）寄存器指令寄存器（InstructionRegister,IR）RISCCISC微處理器的三個(gè)執(zhí)行步驟指令周期（1）取指即從程序存儲(chǔ)器中把PC所指向的指令取出，拷貝到IR；PC+1指向下一條指令的地址；（2）譯指從IR中提取出操作碼，對(duì)指令所要做的操作進(jìn)行翻譯；決定當(dāng)前執(zhí)行那一條指令，跳轉(zhuǎn)到那一個(gè)對(duì)應(yīng)的狀態(tài)去；（3）執(zhí)行指令每一步將在有限狀態(tài)機(jī)的一個(gè)狀態(tài)被執(zhí)行。每個(gè)指令通常在一個(gè)時(shí)鐘周期內(nèi)執(zhí)行有些情況下一些存儲(chǔ)器操作的指令可能需要兩個(gè)甚至更長(zhǎng)的時(shí)鐘周期，這種情況下就需要更多的狀態(tài)來(lái)實(shí)現(xiàn)正確的時(shí)序。一般而言，程序的指令都是存儲(chǔ)在外部寄存器中的，所以除了CPU外，微處理器一般還需要外部存儲(chǔ)器以及連接外部存儲(chǔ)器與CPU的地址以及數(shù)據(jù)總線。810.2微處理器指令集IS指令（Instructions）計(jì)算機(jī)語(yǔ)言里的單詞指令集（InstructionSet）計(jì)算機(jī)的詞匯指令需指明要執(zhí)行的操作和要使用的操作數(shù)機(jī)器語(yǔ)言（MachineLanguage）指令編碼為二進(jìn)制數(shù)格式匯編語(yǔ)言（AssemblyLanguage）符號(hào)格式表示各種指令基本指令加、減和跳轉(zhuǎn)指令9處理器指令架構(gòu)ISAMIPS四個(gè)原則（1）簡(jiǎn)潔規(guī)整;（2）加快經(jīng)常性事件的速度;（3）較小的速度更快;（4）好的設(shè)計(jì)要求良好的妥協(xié)。MIPS,IntelIA32(x86),SunSPARC,PowerPC,IBM390,IntelIA64,ARMTheseareallISAsRISC(ReducedInstructionSetComputer)fixedinstructionlengthfewinstructionformatsload/storearchitecture10MIPSFoundedbyJ.Hennessy(the10thpresidentofStanfordUniversity,1984)MIPS：Microprocessorwithoutinterlockedpipedstages設(shè)計(jì)ARM的原始想法完全來(lái)自于上述MIPS研究小組后來(lái)發(fā)表的論文，兩位優(yōu)秀并敏感的英國(guó)工程師SophieWilson和SteveFurber看到論文后專(zhuān)門(mén)跑到美國(guó)去參觀實(shí)習(xí)了一把，回去后說(shuō)服當(dāng)時(shí)他們的公司老板開(kāi)始設(shè)計(jì)ARM1，這個(gè)ARM1從1983年10月份項(xiàng)目啟動(dòng)，1年半后流片成功。匯編語(yǔ)言加法減法復(fù)雜運(yùn)算11操作數(shù)常數(shù)（Constants）和變量寄存器（register）寄存器組（registerset）寄存器文件（registerfile）寄存器操作MIPS寄存器名稱(chēng)由$符號(hào)開(kāi)頭；變量a、b和c放置在$S0、$S1和$S2；該指令將存在$S1(b)和$S2(C)的32位值相加，32位結(jié)果寫(xiě)入$S0(a)。12MIPS寄存器組13尋址存儲(chǔ)器指令loadwordstorewordMIPS使用字節(jié)可尋址存儲(chǔ)器；存儲(chǔ)器中的每個(gè)字節(jié)都有一個(gè)唯一的地址；14字節(jié)尋址組織方式big-endian或little-endian方式mostsignificantbyte,MSB在左側(cè)leastsignificantbyte,LSB于右側(cè)big-endian機(jī)器字節(jié)的編號(hào)0從大（mostsignificant）端開(kāi)始IBM360,Motorola68K,MIPS,SPARClittle-endian機(jī)器字節(jié)編號(hào)0從小（leastsignificant）端開(kāi)始Intelx86,ARM,DECVax&Alpha,…一個(gè)字有四個(gè)字節(jié)字地址相同15立即數(shù)立即數(shù)操作立即數(shù)是一個(gè)16位二進(jìn)制補(bǔ)碼數(shù)據(jù)；范圍是[-32768，32767]16mips指令格式1）R型------三個(gè)寄存器操作數(shù)格式用于如add和sub指令，有三個(gè)寄存器操作數(shù)。2）I型--------兩個(gè)寄存器操作數(shù)格式用于如lw和sw指令，具有兩個(gè)寄存器操作數(shù)和一個(gè)16位立即數(shù)。3）J型-------無(wú)寄存器格式有一個(gè)26位的立即數(shù)，無(wú)寄存器。

MIPS采用32位指令17機(jī)器語(yǔ)言（machinelanguage）R-typeInstructionsR型是寄存器類(lèi)型（register-type）的縮寫(xiě)32位指令六個(gè)數(shù)字域op，（也稱(chēng)為opcode或操作碼），所有的R型指令的opcode為0；rs，rt，源寄存器rd，目標(biāo)寄存器shamt，只用于移位操作，其它R型指令，shamt為0。funct，（也稱(chēng)為功能碼），確定特定的R型操作每個(gè)字段為五或六比特；18R型指令機(jī)器碼R型指令add和sub的機(jī)器碼匯編指令add$S0,$S1,$S2RS=$S1（17），源數(shù)據(jù)RT=$S2（18），源數(shù)據(jù)結(jié)果存到RD=$S0（16）。19I-TypeInstructions名字I型是立即數(shù)類(lèi)型（immediate-type）的縮寫(xiě)四個(gè)字段op，rs，源操作數(shù)rt，如addi和lw用作目標(biāo)操作數(shù)，sw作為另一種源操作數(shù)；imm，源操作立即數(shù)；rs和imm始終用作源操作數(shù)20I型指令機(jī)器碼21I型指令有一個(gè)16位的立即數(shù)字段，但立即數(shù)是在32位操作中使用的。例如，lw需要在32位的基址寄存器加一個(gè)16位的偏移量。符號(hào)擴(kuò)展如果是正的立即數(shù)，16位立即數(shù)擴(kuò)展為32位，上半部分全為0；如果是負(fù)的立即數(shù)，擴(kuò)展為32位時(shí)上半部分全為1。2的補(bǔ)數(shù)符號(hào)的擴(kuò)展不改變它的值。Signed&UnsignedNumberIfgivenb[n-1:0]inaregisterorinmemoryUnsignedvalueSignedvalue(2’scomplement)22J-typeInstructions名字J型是跳轉(zhuǎn)型（jump-type）的縮寫(xiě)此格式只用跳轉(zhuǎn)指令使用。用單26位的地址操作數(shù)，addr用于指定一個(gè)地址23例將下面的機(jī)器語(yǔ)言代碼翻譯為匯編語(yǔ)言0x2237FFF10x02F34022把每一條指令寫(xiě)成二進(jìn)制，在最高六位查找每個(gè)指令的opcode，opcode決定如何解釋其余位。opcode分別為0010002(810)表示addi和0000002(010)表示R型指令，R型指令的funct字段是1000102（3410），這表明它是一個(gè)sub指令。24微處理器實(shí)例1分析

--------simple4-bitCPUhttp://jaromir.xf.cz/fourbit/fourbit.html25CPUdesignCPUdoessimplethingsmovingdatafrom/tomemorylocationsmakingoperationsonitProgramflowshouldbeallowedtochangeIOlatchesareneededforrealworldoperation

26RegistersRegisters是處理器的基本部件.Theyserveasmostusedandusefulmemorylocations,sourceortargetofmostofinstructions.2774HCT574是8位鎖存器latch，它在WE信號(hào)的上升沿從數(shù)據(jù)總線DB鎖存數(shù)據(jù).利用總線驅(qū)動(dòng)器74HCT245，這個(gè)數(shù)據(jù)能在OE控制下返回到DB總線.Wecanhavealotofregistersonsinglebus,withWEandOEsignalsforeachoneregister.ALU74LS181是4-bitwideALU能執(zhí)行所有常用的logical和arithmetic運(yùn)算.Let'sputtworegisterstogether,add74181andservewithsinglebusdriver.28Wehavetworegisters(AandB),controlledbyrespectiveOEandWEsignalsALU,withoperationcontrolledbysignalsonMandS1toS4signalsBecause74LS181doesn'thavetristateoutputsforconnectingtoDB,busdriverisneededhereSo,datainbothregisters(accessiblefromDB)canbepassedthroughALUandputonDBagain.ALU實(shí)現(xiàn)的功能要實(shí)現(xiàn)：一個(gè)數(shù)據(jù)放在A,另一個(gè)數(shù)據(jù)到B,執(zhí)行ALU運(yùn)算，再把結(jié)果放到A.需要把A數(shù)據(jù)放到bus,變高再變低AWE（鎖存）,然后把B數(shù)據(jù)放到bus,變高再變低BWE.同時(shí),ALU執(zhí)行運(yùn)算(它是組合電路)，結(jié)果在F1toF4輸出.我們需要變高ALUOE，結(jié)果輸出到bus.如果要寫(xiě)到A寄存器,需要變高AWE...butwait.如果我們變高WE,鎖存的數(shù)據(jù)(ALUresult)出現(xiàn)在Aregister的數(shù)據(jù)線,ALU的輸出也改變了，又傳輸?shù)紸寄存器.所以我們需要第三個(gè)register，叫做T-temporaryregister.ALU內(nèi)容輸出到bus：先寫(xiě)到Tregister然后再(whenALUoutputissecurelysaved)到Aregister.29T-registerLoadandStoreM2:loadsourcedatafrombustoTregisterM3=/M1:putdatafromTregisteronDB30T-registerPCprogramcounter–PCIt'smainjobistoincrementwhenevernewinstructionisneededorsettovaluewhenprogramjumpistobemade.31

兩個(gè)級(jí)聯(lián)74HCT193計(jì)數(shù)器,EEPROM存儲(chǔ)器放著program和instructionregister(IR).它存放當(dāng)前instructionbyte直到全部被執(zhí)行.計(jì)數(shù)器的預(yù)置輸入(A,B,CandD)連到BD,為了允許直接改變PC(programjump).否則PC在每個(gè)singleinstruction之后才改變(+1)，byCLOCKUPsignal(pin5).Instructiondecoder,partonePCandregisterswithALUaremusclesofCPU,doinghardwork,butitneedsabraintodecidewhenandhowtochangecontrolsignals.Instructiondecoderdoesthisjob.Nowstartstherealfunandmessingwith74xxlogic.Beforeactuallybuildinginstructiondecoder,itisnecessarytodecidewhichinstructionswearegoingtodecode.32InstructionsForthiscomputer,Idecidedtouseonlythreeinstructions:1,loaddirectdatatoA2,movedatafromsourcetodestination.SourcecanbeA,B,RAMorinputregisters;destinationcanbeA,B,PC,RAMoroutputregisters.3,doALUoperationbetweenAandB,moveresulttoAAllowingPCtoberesultofmoveallowsjumps.YoucantransferinputdatafromIOporttoRAMinsingleinstruction.RAMistreatedasanotherregister,withaddressbusconnectedtoBregister.So,BisaddresspointerforRAMoperation.Somemoveinstructionshavetoaffectonregistersormemory.ExampleismoveAtoA.ThiscouldbeequivalentofNOPinstruction.Thereisnodedicatedindirectaddressingregister,nostack,nointerrupts.33InstructionsMSBofinstructiondetermineswhetherinstructionisLDI.Weneedtowasteonlyonebitforthis,so7bitsareusedasimmediatedata.Asimmediatedataareoneofsourcesforjumpinstructions,thisallowsaddressing128BofprogramROM.Infact,datafromALU(computedjump)canbeusedforjumpingbutthisaddressisonly4bitswide,allowingaddressing16BofROM,leavingthisoptionasnotveryuseful.IfMSBiszero,nextbitdeterminesMOVorALUinstructionnoticehowthisstepbystepdescriptiondeterminesrealoperationofinstructiondecoder.34InstructiontimingInstructionsaredividedintosinglesteps.Inourcase,wewillhaveforsteps,let'scallitmachinecycles.M1:loadinstructiontoIRandputsourcedataonDBM2:loadsourcedatafrombustoTregisterM3:putdatafromTregisteronDBM4:loaddatafromDBtodestination,incrementPC35CLKM1M2M3M4

黑色方塊表示active(高)電平.CLK是輸入時(shí)鐘信號(hào).全指令做完需要eightcycles.InstructionsetInstructionsetissimple:3676543210MOVI1IMMEDIATEDATAMOV00SRCDSTALU01XMS3S2S1S0

If實(shí)際指令是MOVI,源數(shù)據(jù)是lower7bitsfromIR,目標(biāo)destinationisAIf實(shí)際指令是MOV,源數(shù)據(jù)是determinedbyIR[3..5]and目標(biāo)destinationbyIR[0..2]If實(shí)際指令是ALU,源數(shù)據(jù)是fromALUbusdriver,目標(biāo)destinationisAThisgivesusfirstclueaboutinstructionregisteroperation.Notice前沿ofM2comeswhileM1isstillhigh.This重疊isneededto安全寫(xiě)數(shù)據(jù)到Tregister.同樣forM3andM4.CLOCK555時(shí)鐘電路很簡(jiǎn)單.WeneedD-flip-flop,除以2,使clock有4個(gè)可能的狀態(tài).Thosestates解碼bysimpleANDlogic.Toachieve1:1dutycycleofincomingclocksignalfrom555timer,secondD-FFisused.37Instructiondecoder,parttwoKnowingwhatahowtodecode,wecanproceedindesignofinstructiondecoder.Let‘s最復(fù)雜的instruction開(kāi)始,MOV.我們需要選擇源registerduringphaseM1andputonbussoOEsignalof選中的register要有效duringM1phase.我們可以使用74HCT1381-of-8譯碼器.Fortunately它有3個(gè)芯片選擇腳,2個(gè)是反向的.連接thosetwo到IR[7]andIR[6]signals,這樣在MOVinstruction時(shí)有效.Third,highactive,selectpinisconnectedtoM1signal.Thesamegoesforselectingdestinationregister,withtheexceptionthatthirdchipselectpingoestoM4signal.38InstructiondecoderMOVinstructionIC18forSRCIR[5:3]=000

/AOEIR[5:3]=001

/BOEIR[5:3]=011

/MOEIR[5:3]=100

/IAOEIR[5:3]=101

/IBOEIC19forDSTIR[2:0]=000/ASELIR[2:0]=001/BSELIR[2:0]=010/PLIR[2:0]=011/MWEIR[2:0]=100/PAWFIR[2:0]=101/PBWF3976543210MOVI1IMMEDIATEDATAMOV00SRCDSTALU01XMS3S2S1S0Instructiondecoder為了完成MOVinstruction,我們需要小心對(duì)待Tregister.OEofTregisterwillbeactiveduringM3andWEduringM2.MOVIandALUinstructionsareveryalikeexceptofthatfirstoneselectIROEsignal,whileformerselectsALUOEsignalduringM1.AWE(writetoAregister)isactiveduringM4forbothinstructions.4076543210MOVI1IMMEDIATEDATAMOV00SRCDSTALU01XMS3S2S1S0InstructiondecoderIC20,IC21andIC22doesthisjobgeneratesIROEandALUOEsignals,aswellasAWEsignal.ForthispurposeIusedsimplelooking,butusefulsoftware,LogicFriday.IgeneratedthistruthtableforAWEsignal41Decodercircuitoflogicgatesandsoftwareminimizedthistableintoequationsandgeneratedcircuitoflogicgatesdoingthesamejob.42DecodercircuitIdidthesameforIROEandALUOEsignals.Voila,instructiondecoderisdone.Weneedtomakejumpsconditionalinsomeway.IdecidedtouseregisterBforthispurpose.Whenit'scontentis0xF,jump(MOVtoPC)isexecutedasNOP.Notice,onfinalschematics,signalM3isnotusedatall.ItisneededforlatchingoutputofTregister,butM1isused,asdriverexpectsnegativelogicandM3isonlyinvertedM1.4344DataMemoryBregistertoAddressDataIOtoDBM1:putsourcedataonDBM2:loadsourcedatafrombustoTregisterM3:putdatafromTregisteronDBM4:loaddatafromDBtodestination45DatamemoryInput/outputportsTheonlythingnotdescribedfornowisIOpart.Wehavetwosignalsfrom138decoders,soallisneededisdouble4-bitbusdriver(IC25)forinputportsandtwo4-bitwidelatchesasoutputports(IC26,IC27).46ALLSCHEMATIC47AddressA=000；

寄存器地址B=001；IA=100；

外部輸入IB=101；MEM=011；存儲(chǔ)器訪問(wèn)PA=100；

外部輸出PB=101；PC=010；

程序地址（指針）48ProgrammingAsourCPUisbasicallydone,weneedtoprogramittomakesomethinguseful.Letsstartwithsimpleprogram-emulationoffourNANDgates.

MOVIA,A0b00100000;movedatafrominputAtoregisterA

MOVIB,B0b00101001;movedatafrominputBtoregisterB

ALUNAND

0b01010100;doNANDoperation{not(A&B)A}

MOVA,PA0b00000100;movedatafromA(ALUresult)toportA

MOVI0

0b10000000;movezerotoA

MOVA,B0b00000001

;movethiszerotoB

MOVA,PC0b00000010;jumptozero4976543210MOVI1IMMEDIATEDATAMOV00SRCDSTALU01XMS3S2S1S0AssemblyQuickhandassemblygivesthisoutput0x200x290x540x040x800x010x0250Burning燒錄代碼ThatisreadytobeburnedintoEEPROM.IusedGeniusG540programmerreallylowcost,butitdoesitsjob.51Result,or7400^2to7400^xCircuitwasbuiltonperfboardwithdimensioncca18x18cm.Currentconsumptionisabout180mA,majorityofthisisdrawnby74181and74175inplainoldTTLtechnology.ClockspeedisdeterminedbyC1capacitor.For1uF,clockgeneratorticksatabout80Hz,giving10Hzexecutionspeed.Fornocapacitor,oscillatorworksatfrequencygivenbystraycapacitance,resultingincca57kHzexecutionspeed.Yes,whopping57,000instructionspersecond.52微處理器完整電路53數(shù)據(jù)通路、控制單元電路（控制和狀態(tài)信號(hào)）Another4-bitTTLCPU54TheReducedInstructionSet-APOLLO181

only2^4=16operationcodes(orop-codes)Eachinstructionthentakesanargumentof4-bitdataasimmediateoperandNotesforthe4-bitimmediateoperands:§"n"isa4-bitbinarydata§"r"pointsoneofthe16registers§"p"isabinaryoperandwhichreferstothefourfunction–selectlines(S0,S1,S2,S3)oftheALUitincludesAddition,Subtraction,Shiftoperand,MagnitudeComparisonplustwelveotherArithmeticoperations.Thenitincludes

Exclusive-OR,Comparator,AND,NAND,OR,NORplustenotherLogicOperations§"s"canonlytakethebinaryvaluesof“0000”(0Hex)or“1111”(FHex)55NewInstructionset56InstructionOpCodeSummaryDescriptionLOAD(Mem)0000Accum=mem[Operand];LoaddatatotheaccumulatorfromavalueheldinRAMwiththeaddresssetbytheoperand.

LOAD(Value)0001Accum=Operand;Loadtheoperanddatatotheaccumulaor.ADD(Mem)0010Accum+=mem[Operand];AddvalueheldinmemorytotheaccumuatorADD(Value)0011Accum+=Operand;Addoperandtotheaccumuator

SUB(Mem)0100Accum-=mem[Operand];Subtractvalueheldinmemoryfromtheaccumuator

SUB(Value)0101Accum-=Operand;Subtractoperandfromtheaccumuator

STO(Mem)0110mem[mem[Operand]]=Accum;

Storeaccumulator'svaluetomemory,addressheldinmemory.

STO(Value)0111mem[Operand]=Accum;Storeaccumulator'svaluetomemory,operandequalsaddress.

READ(Mem)1000Addr=mem[Operand];Readfromaddress,addressheldinmemory.READ(Value)1001Addr=Operand;

Readfromaddress,operandequalsaddress.JMPLOW(Mem)1010PCLowAddr=mem[Operand]Jumpthelower4-bitsoftheProgramCountertoanaddressheldinmemory.JMPLOW(Value)1011PCLowAddr=OperandJumpthelower4-bitsoftheProgramCountertoanaddressheldbytheoperand.JMPHIGH(Mem)1100PCHighAddr=mem[Operand]

Jumptheupper4-bitsoftheProgramCountertoanaddressheldinmemory.

JMPHIGH(Value)1101PCHighAddr=Operand

Jumptheupper4-bitsoftheProgramCountertoanaddressheldbytheoperand.JMPZERO(Mem)1110if(Accum==0){

PC=mem[Operand];

}Ifaccumulatorequalszero,programcounteraddressequalsavalueinprogrammemory.JMPZERO(Value)1111if(Accum==0){

PC=Operand;

}Ifaccumulatorequalszero,programcounteraddressequalstheoperand.

NewInstructionsetTheMath(Command#4,#5,#6,#7,#8,#9)Movedatainsideandoutside(Command#1,#2,#3,#E,#F)ComparisonandJump(Command#0,#A,#B,#C,#D)57MicrocodeTheop-codeoftheinstructionisdecodedimmediatelybytheROM(74188)becausethemostsignificantdata-outputsoftheRAMarehard-wiredtotheROMaddresses.Foreach

op-codetheROMprovidesamicroprogrammed

sequenceoffourstates.Sixteendifferentop-codeswithfourstateseachmakesixty-fourpossiblecombinations.Thus

four

ROM74188are

tiedtogethertoformalargerarrayofmemorythatconsistsof

64words.58Schematicformicrocode594bitCPU-Micro-instructionmicrocodedetailStartingataddresszeroandincrementingbyoneforeachline,fourforeachinstruction60ADDRESSROM0ROM10FFFF17FFF2BFFF3FFFF4FFFD5DFFF6FFFF7FFFD8FFFB9DFFF10FFFF11FFFB12FFFF13FDFF14FFFF15FFFF16FFFF17EFFF18FFFF19FFFF20FFFF21F7FF22FFFF23FFFF24FFFF25FBFF26FFFF27FFFF28FFFD29FEFF30FFFF31FFFD32FFFB33FEFF34FFFF35FFFB36FFFF37FFEF38FFFF39FFFF40FFFF41FF7F42FFEF43FFFF44FFFF45FFBF46FFEF47FFFF48FFFF49FFDF50FFEF51FFFF52FFFE53DFFF54FFFF55FFFE56FFFB57FFF758FFFF59FFFB60FFFF61FFFF62FFFF63FFFFLTCHINC/LD/INC/DECLTCH/WRLTCH/RSTLTCH/RDINS/EROMINSPCACCACCACCREGREGFLAGJMPLJMPEJMPGPCOUTREGDATAIN01FETCH1111111111111111FFFF01111111111111117FFF1011111111111111BFFF1111111111111111FFFFLIT1111111111111101FFFD1101111111111111DFFF1111111111111111FFFF1111111111111101FFFDLOAD1111111111111011FFFB1101111111111111DFFF1111111111111111FFFF1111111111111011FFFBSTORE1111111111111111FFFF1111110111111111FDFF1111111111111111FFFF1111111111111111FFFFINC1111111111111111FFFF1110111111111111EFFF1111111111111111FFFF1111111111111111FFFFInterruptInterruptsignalsserveinAPOLLO181thesamepurposesasinterruptsinothersmicroprocessorswhenanexternalasynchronouseventhasoccurred,theCPUjumptoanotherportionoftheprogram.Asimplenon-maskableinterrupttechniquehasbeenimplementedviahardware.Whenadeviceassertstheinterruptsignal(inoursimplecaseabuttonkey)theCPUwaitstofinishthecurrentinstructionexecutionandthendefinitelyjumpsatthememorylocationpointedbyasetof8-bitswitchesplacedontheboard.Inthiswayitistheoreticallypossibletoimplement2^8=256differentinterruptswhichcouldpointall256RAMlocationsoftheprogramspace.Herewecanputaconditionaljumptabletoenhanceinterruptcapability.Unfortunatelythelackofamemorystackandthelimitednumberofavailableinstructionshaspreventedtheimplementationofa“returnfrominterrupt”whichwouldhaveallowedtheprogramtoflowbacktothemainprogramwhereitwasinterrupted.61ComputerOrganizationComputerdesignasanapplicationofdigitallogicdesignproceduresComputer=processingunit+memorysystemProcessingunit=control+datapathControl=finitestatemachineInputs=machineinstruction,datapathconditionsOutputs=registertransfercontrolsignals,ALUoperationcodesInstructioninterpretation=instructionfetch,decode,executeDatapath=functionalunits+registersFunctionalunits=ALU,multipliers,dividers,etc.Registers=programcounter,shifters,storageregisters62總結(jié)63ALU時(shí)鐘PC計(jì)數(shù)器寄存器程序存儲(chǔ)器寄存器組總線LDassertedduringalo-to-hiclock

transitionloadsnewdataintoFFsOEassertedcausesFFstatetobe

connectedtooutputpins;otherwisethey

areleftunconnected(highimpedance)OEQ7Q6Q5Q4Q3Q2Q1Q0LDD7D6D5D4D3D2D1D0CLKRegistersSelectivelyloaded–ENorLDinputOutputenable–OEinputMultipleregisters–

group4or8inparallel64RDWRA9A8A7A6A5A4A3A2A2A1A0IO3IO2IO1IO0MemoriesLargerCollectionsofStorageElementsImplementednotasFFsbutasmuchmoreefficientlatchesHigh-densitymemoriesuse1-5switches(transitors)perbitStaticRAM–1024wordseach4bitswideOncewritten,memoryholdsforever(nottruefordenserdynamicRAM)Addresslinestoselectword(10linesfor1024words)ReadenableSameasoutputenableOftencalledchipselectPermitsconnectionofmany

chipsintolargerarrayWriteenable(sameasloadenable)Bi-directionaldatalinesoutputwhenreading,inputwhenwriting651616ABSZNOperation16DataPath(ALU)ALUBlockDiagramInput:dataandoperationtoperformOutput:resultofoperationandstatusinformation6616ZNOP8ACREG1616loadpathstore

pathDataMemory(16-bitwords)16OP16PCIR1616dataaddrrdwrMARControl

FSMBlockDiagramofProcessorRegisterTransferViewofPrincetonArchitectureWhichregisteroutputsareconnectedtowhichregisterinputsArrowsrepresentdata-flow,otherarecontrolsignalsfromcontrolFSMMARmaybea