信息與通信Cadence實驗系列RTL編譯和束縛

RTLcompiler(RC)IntroductionRoleinICdesignGUIinterfaceSynthesisflowIntroductionRCisafast,highcapacitysynthesissolutionfordemandingchipdesigns‘Globalfocusedsynthesis’resultsinrapidtimingclosureIntroduction綜合是前端設(shè)計的重要步驟HDL代碼翻譯成門級網(wǎng)表netlist約束條件（達到面積，時序等參數(shù)標準）需特定工藝庫評價標準：面積，速度，功耗SynthesistoolIC設(shè)計綜合工具包括SynopsisDC和CadenceRC；在FPGA端，常用的綜合工具有Synplicitysynplify和XilinxXSTSynthesis綜合的過程分為兩步，首先將HDL描述語言翻譯成與工藝庫無關(guān)的門級網(wǎng)表文件，然后通過綜合工具優(yōu)化，映射到跟具體工藝庫相關(guān)的門級網(wǎng)表。RTLcompiler(RC)IntroductionRoleinICdesignGUIinterfaceSynthesisflowRoleinICdesign前端設(shè)計規(guī)格制定詳細設(shè)計HDL編碼仿真驗證邏輯綜合ICprocess

Advantage時序收斂的全局綜合工具提高芯片性能縮短設(shè)計時間提供高質(zhì)量的硅片（Qos）RTLcompiler(RC)IntroductionRoleinICdesignGUIinterfaceSynthesisflowStartGUI命令符：rc-guiGeneralViewManubarLogicalviewerHDLviewerSchematicviewerPhysicalviewerManubarManubarLogicalviewerandHDLvewerSchematicviewerRTLcompiler(RC)IntroductionRoleinICdesignGUIinterfaceSynthesisflowSynthesisflowInvoketheRCSpecifythelibraryLoadHDLfilesPerformElaborationApplyconstraintsSynthesizeSavedesignAnalyzeSynthesisflowset_attributelib_search_path<full_path_of_technology_library_directory>/set_attributehdl_search_path<full_path_of_hdl_files_directory>set_attributelibrary<technology_library>/read_hdl<hdl_file_names>elaborate<top_level_design_name>setclock[define_clock–period<periodicity>–name<clock_name>[clock_ports]]external_delay–input<specify_input_external_delay_on_clock>external_delay–output<specify_output_external_delay_on_clock>synthesize-to_mappedreporttiming><specify_timing_report_file_name>reportarea><specify_area_report_file_name>write–mapped><specify_netlist_name>write_script><script_file_name>Step1InvoketheRCrc－guiStep2Specifythelibrary設(shè)置工藝庫存放路徑set_attributelib_search_path/export/home1/STSY_BB/BB_y29/lib/Synopsys指定要加載的工藝庫set_attributelibrary{hjtc18_tt.lib}Step3LoadHDLfilesLoadMipssourcesread_hdl/export/home1/STSY_BB/BB_y29/mips_source/MCore.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/alu_v2.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/biu.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/branch.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/core.vread_hdl…….tclscriptStep4PerformElaborationBuildsdatastructuresInfersregistersinthedesignPerformshigher-levelHDLoptimization,suchasdeadcoderemovalCheckssemanticsStep4PerformElaborationElaborate

建立一個結(jié)構(gòu)級描述，該描述與工藝無關(guān)SchematicviewerStep5ApplyConstraintsConstraintCommandsdefine_clock定義時鐘輸入波形external_delay設(shè)定輸入輸出相對時鐘的延時path_delay設(shè)置路徑時序約束其他：create_mode,define_cost_groud,multi_cycleStep6SynthesizesetMAP_EFFhighsynthesize-to_mappedeff$MAP_EFF-no_incrStep7Savedesign保存綜合的網(wǎng)表文件write-mapped>MCore_synth.v保存約束文件（sdc）write_sdc>MCore_tst.sdcStep8Analyze輸出功耗報表文件reportpower>MCore.power.rpt輸出時序報表文件reporttiming>MCore.timing.rptStep8Analyzetimingandpowertclscript--命令行批量處理set_attributelib_search_path/export/home1/STSY_BB/BB_y29/lib/Synopsys##Thisdefinesthelibrariestouseset_attributelibrary{hjtc18_tt.lib}read_hdl/export/home1/STSY_BB/BB_y29/mips_source/MCore.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/alu_v2.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/biu.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/branch.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/core.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/cp0.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/decode.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/exec.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/fifo.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/idtlb.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/irq.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/jtlb.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/mcore_define.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/mdu_v2.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/mem_stage.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/mmu.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/pag.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/pipeline.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/reg_ctrl.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/regfile.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/shifter.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/tlb.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/tlb_page.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/trap.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/write_back.vtclscript##Thisbuilsthegeneralblocekelaborate##thisallowsyoutodefineaclockandthemaximumallowabledelays##READMOREABOUTTHISSOTHATYOUCANPROPERLYCREATEATIMINGFILEdefine_clock-nameclk-period5000[find/-portclk]external_delay-input100-clock[find/-clockclk]-edge_fall[all_inputs]external_delay-output100-clock[find/-clockclk]-edge_fall[all_outputs]set_attributewireload_modeenclosedset_attributemax_dynamic_power0.0MCoreset_attributemax_leakage_power0.0MCore##ThissynthesizesyourcodesetMAP_EFFhighsynthesize-to_mapped-eff$MAP_EFF-no_incr##Thiswritesallyourfiles##changethetsttothenameofyourtoplevelverilog##CHANGETHISLINE:CHANGETHE"accu"PARTREMEMBERTHIS##FILENAMEYOUWILLNEEDITWHENSETTINGUPTHEPLACE&ROUTEwrite-mapped>MCore_synth.v##THESEFILESARENOTREQUIRED,THESDCFILEISATIMINGFILE##write_script>scriptwrite_sdc>MCore_tst.sdc##reportandannlyzepowerandtimingreportpower>MCore.power.rptreporttiming>MCore.timing.rptEncounterconformalIntroductionEC’necessaryProcessflowIntroductionEC是等效功能驗證工具，即驗證寄存器級電路和映射后的門級電路是否等效對龐大而復(fù)雜的設(shè)計，仿真速度不再是主要的驗證流程評估基準高級驗證流程以互補的方式確保邊際錯誤情況被及時發(fā)現(xiàn)Introduction頭號設(shè)計瓶頸-驗證設(shè)計的整體復(fù)雜性不斷增強，設(shè)計驗證任務(wù)也隨之變得復(fù)雜，硬件驗證本身越來越具有挑戰(zhàn)性，驗證時間正在變得越來越長調(diào)查表明，只有39%的設(shè)計在第一次硅驗證時沒有缺陷，60%包含邏輯或功能缺陷，20%以上需要三次或者多次硅驗證。另外一項Collett調(diào)查還表明，全部工程時間的約50%是驗證時間。EncounterconformalIntroductionEC’necessaryProcessflowEC’necessary

綜合出的門級網(wǎng)表與RTL設(shè)計在邏輯和時序上應(yīng)完全一致。但是某些書寫風(fēng)格和設(shè)計思路卻會造成兩者不一致的情況?？聪旅娴睦樱ú煌暾舾斜恚㎡neexamplemoduleOR_GATE_A(OUT_A,IN1,IN2);outputOUT_A;inputIN1,IN2;regOUT_A;always@(IN1orIN2)