文稿介紹08驗證課systemverilog verification spec

SpecificationforDesignUnderTest(DUT)forLaboratorySTAGESTAGE

Figure1:TopLevelBlockdiagramofsystemanddescriptionofTheDUTconsistsofatwostagespipelhatconsistsofanExecutepre-processorandanALUbasedonamodificationtotheDLXISA.ThepreprocessorperformsthefunctionofthepreparationofthedesigninputsandcontrolsfortheALUusingtheinformationseenattheinput.TheALUthenexecutestherelevantoperationonthe ingd ontrolledbytheopselect,operationandshift_numbervalues.Eachunitistlyclockedandreset.Almostallvalidinstructionsunderconsiderationpassthroughboththe ceptformemorywriteinstructionswhichdealwiththemem_data_wr_enandmem_data_write_outsignalandcomple yskiptheALUstage.Thus,whenenabledthefirststagecreatesthealuin1,aluin2,operation,opselect,shift_number,enable_arithandenable_shiftvalues.ThesevaluesarethenusedbytheALUstagetocreatetherelevantaluoutandcarrysignals.SYSTEMCombinationalBehaviorof Reset

(opselect==`MEM_WRITE)&&(immp_regn_op==1)Allsequentialoutputsgoto0i.e.aluin1,aluin2,operation_out,opselect_out,shift_number,enable_arithandenable_shiftforStage1andaluoutandcarryforstage2goto0.NormalBehaviorofEXECUTEPREPROCESSORAllsequentialoutputschangeonlywhenenable_ex==1.Therefore,enable_ex==1,thefollowingtruthtablesholdforeachsequential0Nochange10XXNO101110NO11FORALLOTHERCOMBINATIONSaluin2REMAINS0Nochange10Nochange10XX01011FORALLOTHERCOMBINATIONSshift_numberIS0XX0101111100111FORALLOTHERCOMBINATIONSenable_arithIS0X011FORALLOTHERCOMBINATIONSshift_numberISNormalBehaviorofALUAllthecommandsarevalidonlywhentherelevantenablesi.e.enable_arith==1orenable_shift==1andtheentiresystemissensitivetothepositiveedgeoftheclock.Assuming,thatenable_execute==1,thefollowingtruthtablesholdgoodforeachALU.PleasenotethattheinportoftheShiftALUisconnectedtoaluin1.0XNO1in<<shift;0paddedlower1in<<shift;0paddedlower1in>>shift;0paddedupper1in>>shift;signextendedupperFORALLOTHERCOMBINATIONSaluoutREMAINSaluout={carry,0XX1Signedaluin1(+)1{h_carry,h_add[15:0]}=aluin1[15:0]carry=h_carry;aluout=1Signedaluin1(-)1(BITWISENOT)aluin2;carry=1aluin1(BITWISEAND)1aluin1(BITWISEOR)1aluin1 OR)1aluout[31:16]=aluout[15:0]=16'h0;carry=1signext{aluin2[7:0]};carry=1zeropad{aluin2[7:0]};carry=1signext{aluin2[15:0]};carry=1zeropad{aluin2[15:0]};carry=1aluin2;carry=1aluin2;carry=FORALLOTHERCOMBINATIONSaluoutandcarryREMAINAdditionalUnderstandingsignext{}:(NotethatM>out[M:0]=signext{in[N:0]}willperform:out[N:0]=in[N:0]Understandingzeropad{}:(NotethatM>out[M:0]=zeropad{in[N:0]}willperform:out[N:0]=in[N:0]CarryThecarryoutfromtheExecuteunitfunctionsperarithmeticcorrectnessforSubtractionandAddition.Forthefollowingoperationsthecarry=Arithmetic:AND,OR,XOR,Shiftoperations:SHLEFTLOG,SHRGHTLOG,ForSHLEFTART(ShiftLeftifyoustartoffwithanegativenumberi.e.in[31]==1,andifyoudoaARITHMETICleftshiftonthisnumber(sayin<SHLEFTART>4)thencarry=1.Ifyoustartoffwithapositivenumberi.e.in[31]==0,thenthecarry=Theaimistopreservetheinitialsignvalueofthevaluebeingshiftedsoth heckcanbemadetoseeifthesignoftheresultingnumberhaschanged.Appendix1// // //DATA (DUT)immp_regn中的簡介控制圖1：系統(tǒng)頂層框圖和control_in描述DUT由兩級管道組成，該管道由執(zhí)行預處理器和基于DLXISA修改的ALU組成。預處理器使用輸入處看到的信息會經(jīng)過這兩個階段，除了處理mem_data_wr_en和mem_data_write_out信號并完全跳過ALU階段的內(nèi)存寫指令外。因此，當啟用時，第一級創(chuàng)建aluin1、aluin2、operation、opselect、shift_number、enable_arithenable_shift，ALU創(chuàng)建相關的aluout和進位信號。01opselect==`MEM_WRITE)&&(immp_regn_op==0，1aluin1、aluin2、operation_out、opselect_out、shift_number、enable_arith和enable_shift，階段2的aluout和進位變?yōu)?。2.3EXECUTEPREPROCESSORBLOCK0無變化(NC)1enable_exopselectcontrol_in[3]aluin20XX沒有變化1.ARITH_LOGIC01ARITH_LOGIC11MEM_READ01MEM_READ1mem_data_read_inaluin2operation_outopselect_outenable_exoperation_out010無變化(NC)1shift_numberenable_exopselectimm[2]1.SHIFT_REG01.SHIFT_REG1對于所有其他組合，shift_number啟用_arith_exopselectcontrol_in[3]_arith1.ARITH_LOGIC01.ARITH_LOGIC11.MEM_READ01.MEM_READ1對于所有其他組合，enable_arith為0啟用_shift_exopselect_shift1.SHIFT_REG對于所有其他組合，shift_number2.4ALUBLOCKclckResetaluin1aluin2peratinpselectshift_numberenable_arithenable_shift所有命令僅在相關使能（即enable_arith==1enable_shift==1）且整個系統(tǒng)對時鐘上升沿敏感時才有效。假設enable_execute1ALU。請注意，ShiftALUSHIFT_ALUshift_operation[1:0]aluout0X沒有變化1SHLEFTLOGin；01SHLEFTART01SHRGHTLOGin01SHRHTARTaluoutARITH_ALU用aluopselect操作aluout={carry,aluout[31:0}0XX1ARITH_LOGICADDaluin11ARITH_LOGICHADD{h_carry,h_add[15:0]}aluin1[15:0]aluin2[15:0]h_carry;aluout=sxt(h_add)1ARITH_LOGICSUBaluin11.ARITH_LOGICNOT（按aluin2；進位1ARITH_LOGICaluin1（按位與）1ARITH_LOGICaluin1（按位或）1ARITH_LOGICaluin11ARITH_LOGICLHGaluout[31:16]aluin2[15:0aluout[15:0]16'h01MEM_READLOADBYTESignext{aluin2[7:0]1MEM_READLOADBYTEUZeropad{aluin2[7:01MEM_READLOADHALFsignext{aluin2[15:01MEM_READLOADHALFUZeropad{aluin2[15:0]};進位MEM_READLOADWORDaluin2;進位MEM_READaluin2;進位對于所有其他組合，aluoutCarryout[M:0]signext{in[N:0]}out[N:0]in[N:0]out[M:N+1][N]out[M:0]Zeropad{in[N:0]}out[N:0]in[N:0]out[M:N+1]0算術：AND、OR、XOR、LHGMEM_READc．移位操作：SHLEFTLOG、SHRGHTLOG、對于SHLEFTART（算術如果你以負數(shù)開始，即in[31]==1，并且如果你對此數(shù)字進行算術例如在中），=1bin[31]00附錄1DEFINITIONS定義CLK_PERIOD10REGISTER_WIDTHINSTR_WIDTHIMMEDIATE_WID