NS ADC16V130低IF接收器參考設(shè)計(jì)

NSADC16V130低IF接收器參考設(shè)計(jì)NS公司的ADC16V130是LVDS輸出的16位130MSPS高性能ADC,雙電源1.8V和3.0V工作,16位分辨率,取樣速率130MSPS,滿功率帶寬1.4GHz,160-MHz的SNR為76.7dB,SFDR為90.6dBFS,主要應(yīng)用在高IF取樣接收器,多載波基站接收器,測試測量設(shè)備,通信基礎(chǔ)設(shè)備,數(shù)據(jù)采集和手提儀表等.本文介紹了ADC16V130主要特性,方框圖,低頻和高頻變壓器驅(qū)動電路以及SP16130CH4RB低IF接收器參考設(shè)計(jì)主要特性,詳細(xì)電路圖和材料清單(BOM).

ADC16V130:16-Bit,130MSPSA/DConverterwithLVDSOutputs

TheADC16V130isamonolithichighperformanceCMOSanalog-to-digitalconvertercapableofconvertinganaloginputsignalsinto16-bitdigitalwordsatratesupto130MegaSamplesPerSecond(MSPS).Thisconverterusesadifferential,pipelinedarchitecturewithdigitalerrorcorrectionandanonchipsample-and-holdcircuittominimizepowerconsumptionandexternalcomponentcountwhileprovidingexcellentdynamicperformance.Automaticpower-upcalibrationenablesexcellentdynamicperformanceandreducespart-to-partvariation,andtheADC16V130couldbere-calibratedatanytimebyassertingandthende-assertingpower-down.Anintegratedlownoiseandstablevoltagereferenceanddifferentialreferencebufferamplifiereasiesboardleveldesign.On-chipdutycyclestabilizerwithlowadditivejitterallowswidedutycyclerangeofinputclockwithoutcompromisingitsdynamicperformance.Auniquesample-and-holdstageyieldsafullpowerbandwidthof1.4GHz.ThedigitaldataisprovidedviafulldatarateLVDSoutputs–makingpossiblethe64-pin,9mmx9mmLLPpackage.TheADC16V130operatesondualpowersupplies+1.8Vand+3.0Vwithapower-downfeaturetoreducethepowerconsumptiontoverylowlevelswhileallowingfastrecoverytofulloperation.

ADC16V130主要特性:

■DualSupplies:1.8Vand3.0Voperation

■Onchipautomaticcalibrationduringpower-up

■Lowpowerconsumption

■Multi-levelmulti-functionpinsforCLK/DFandPD

■Power-downandsleepmodes

■Onchipprecisionreferenceandsample-and-holdcircuit

■Onchiplowjitterduty-cyclestabilizer

■FulldatarateLVDSoutputport

■64-pinLLPpackage(9x9x0.8,0.5mmpin-pitch)

ADC16V130主要指標(biāo):

■Resolution16Bits

■ConversionRate130MSPS

■SNR

(fIN=10MHz)

(fIN=70MHz)

(fIN=160MHz)

78.5dBFS(typ)

77.8dBFS(typ)

76.7dBFS(typ)

■SFDR

(fIN=10MHz)

(fIN=70MHz)

(fIN=160MHz)

95.5dBFS(typ)

92.0dBFS(typ)

90.6dBFS(typ)

■FullPowerBandwidth1.4GHz(typ)

■PowerConsumption

Core

LVDSDriver

Total

650mW(typ)

105mW(typ)

755mW(typ)

■OperatingTemperatureRange-40°C~85°C

ADC16V130應(yīng)用:

■HighIFSamplingReceivers

■Multi-carrierBaseStationReceiversGSM/EDGE,CDMA2000,UMTS,LTEandWiMax

■TestandMeasurementEquipment

■CommunicationsInstrumentation

■DataAcquisition

■PortableInstrumentation

圖1.ADC16V130方框圖

圖2.ADC16V130低頻輸入變壓器驅(qū)動電路

圖3.ADC16V130高頻輸入變壓器驅(qū)動電路

圖4.ADC16V130內(nèi)部基準(zhǔn)和去耦電路

SP16130CH4RB參考設(shè)計(jì)板

TheSP16130CH4RBReferenceBoarddemonstratesalowIFreceiversubsystemapplicationincludinganADC16V130analog-to-digitalconverter(ADC)andLMK04031Bclockconditionerwhichprovidesdigitizationandclockingasusedinwirelessinfrastructuresystems.

Thissubsystemreferencedesignprovidessingletodifferentialconversionandlowpassfilteringoftheinputsignalwithanoptimized,double-balunnetworkandhighdynamicrangedigitizationtoparallelLVDSoutputsusingtheADC16V130.The125MHzlow-jitter,LVPECLclocksignalfortheADCisgeneratedbyaLMK04031Bclockconditionerwhichdemonstrateslessthan250fsoftotaljitterovertheinputbandwidthoftheADC.

ThemeasuredsystemperformancedemonstratesalargesignalSNRof75.8dBFSandSFDRgreaterthan84dBFSfora-1dBFS,52MHzinputsignalandasamplingfrequencyof125MSPS.Forsmallsignals,theperformanceimprovesto78.0dBFSSNRandgreaterthan94dBFSSFDR.

EvaluationofthisreferenceboardissimplifiedwiththeWaveVision5.1DataCaptureBoardandWaveVision5software.

SP16130CH4RB低IF接收器參考設(shè)計(jì)板主要特性:

KeyFeaturesoftheSP16130CH4RBLowIFReceiverReferenceDesignBoard

■Demonstratesasubsystemarchitectureusedinwirelessinfrastructuresystemsand

frequencydomainanalyzers

■Configuredforinputfrequenciesbetween5and52MHz

■Boardcomesfullyassembledandtested

■Single(+5V)supplyneeded

■AllADCfeaturescanbeexercised

■FeaturedProductsInclude:

—ADC16V13016-bit,130Megasamplepersecond(MSPS)ADCwithparallelLVDSoutputs

—LMK04031Blow-jitterprecisionclockconditionerconsistingofcascadedphaselockedloops(PLLs),aninternalvoltagecontrolledoscillator(VCO)andadistributionstage

—Severalenergy-efficientpowermanagementICs

■Large-signal(-1dBFS)performancefora52MHzinputsignal:

—SNR=75.8dBFS

—SFDR>84dBFS

■Small-signal(-20dBFS)performancefora52MHzinputsignal:

—SNR=78.0dBFS

—SFDR>94dBFS

■Totalintegratedjitter<250fs

■PICLoaderboardincludedwithreferenceboardforquickandeasyconfigurationoftheLMK04031B

■CompatiblewiththeWaveVision5.1DataCaptureBoardandWaveVisio