基于FPGA任意倍數(shù)分頻器畢業(yè)設(shè)計(jì)

基于FPGA任意倍數(shù)分頻器設(shè)計(jì)目錄1緒論ff0圖3.6半整數(shù)分頻原理圖只有當(dāng)35譯碼器的輸出選中偶數(shù)分頻且rst=1時(shí)半整數(shù)分頻才工作。半整數(shù)分頻實(shí)現(xiàn)的程序見(jiàn)附錄A3。半整數(shù)分頻（6.5分頻）模塊程序仿真結(jié)果如圖3.7所示：圖3.7半整數(shù)分頻從仿真結(jié)果可以看出： 本設(shè)計(jì)的優(yōu)點(diǎn)是：在rst或者sel有一個(gè)為低電平時(shí)，計(jì)數(shù)器停止計(jì)數(shù)，維持上一狀態(tài)輸出，當(dāng)rst和sel都為高電平的時(shí)，重新開(kāi)始計(jì)數(shù)，執(zhí)行分頻。3.4.4占空比可調(diào)的分頻模塊設(shè)計(jì)占空比可調(diào)的分頻模塊根據(jù)撥碼開(kāi)關(guān)選擇占空比（m1：n1），對(duì)輸入的clk信號(hào)進(jìn)行占空比可調(diào)的分頻。本設(shè)計(jì)占空比可調(diào)的分頻的關(guān)鍵是對(duì)clk信號(hào)的上升沿信號(hào)進(jìn)行計(jì)數(shù)temp。當(dāng)temp<m1時(shí)clkout2輸出1，否則輸出0，從而實(shí)現(xiàn)占空比可調(diào)的分頻。只有當(dāng)35譯碼器的輸出選中偶數(shù)分頻且rst=1時(shí)占空比可調(diào)的分頻才工作。占空比可調(diào)的分頻實(shí)現(xiàn)的程序見(jiàn)附錄A4。占空比可調(diào)的分頻（1:3分頻）模塊程序仿真結(jié)果如圖3.8所示：圖3.8占空比可調(diào)分頻從仿真結(jié)果可以看出： 這種設(shè)計(jì)的優(yōu)點(diǎn)是：在rst或者sel有一個(gè)為低電平時(shí)，可以保持前一狀態(tài)和計(jì)數(shù)結(jié)果，使其具有記憶功能。在恢復(fù)工作時(shí)，繼續(xù)計(jì)數(shù)，具有有良好的性能。3.4.5小數(shù)分頻模塊設(shè)計(jì)小數(shù)分頻模塊根據(jù)撥碼開(kāi)關(guān)選擇分頻系數(shù)（n.x），對(duì)輸入的clk信號(hào)進(jìn)行小數(shù)分頻。本設(shè)計(jì)小數(shù)分頻的關(guān)鍵是實(shí)現(xiàn)（10-x）次n分頻和x次的n+1分頻的交替進(jìn)行，從而實(shí)現(xiàn)小數(shù)的分頻。只有當(dāng)35譯碼器的輸出選中偶數(shù)分頻且rst=1時(shí)占空比可調(diào)的分頻才工作。小數(shù)分頻實(shí)現(xiàn)的程序見(jiàn)附錄A5.小數(shù)分頻（1.3分頻）模塊程序仿真結(jié)果如圖3.9所示：圖3.9小數(shù)分頻從仿真結(jié)果可以看出： 這種設(shè)計(jì)的有優(yōu)點(diǎn)是:在rst或者sel有一個(gè)為低電平時(shí)，可以保持低電平輸出，并保持計(jì)數(shù)。在恢復(fù)工作時(shí)，繼續(xù)計(jì)數(shù)，具有有良好的性能。3.4.6encoder_35模塊的設(shè)計(jì)encoder_35模塊的功能見(jiàn)表：表3.1encoder_35模塊的功輸入信號(hào)輸出信號(hào)pqvabcde0000000100100010010001000110100010010000101000001100000011100000例如：當(dāng)p=0,q=0，v=0時(shí)，e端輸出高電平1，而其他輸出低電平0，表明e端被選中。encoder_35模塊的作用是：提供給mux51模塊的輸入信號(hào)，mux51模塊根據(jù)輸入信號(hào)，判斷是哪路信號(hào)后輸出信號(hào)。encoder_35模塊實(shí)現(xiàn)的程序見(jiàn)附錄A6encoder_35模塊程序仿真結(jié)果如圖3.10所示：圖3.10encoder_35仿真圖該仿真是通過(guò)設(shè)置p=0，q=0，v=0，來(lái)實(shí)現(xiàn)的，結(jié)果為e=1，其余為0；3.4.7led模塊的設(shè)計(jì)數(shù)碼管接成共陽(yáng)極，只有當(dāng)?shù)碗娖綍r(shí)才有效。Led-out為段選信號(hào)，led-bie為位選信號(hào)。m，n，op，q，v根據(jù)輸入的信號(hào)，選擇a5，b5，c5，d5的結(jié)合形式。具體功能如下：表3.2led模塊功能輸入信號(hào)結(jié)合形式p(m)q(n)v(o)000x=8*d5+4*c5+2*b5+1*a5001x=8*d5+4*c5+2*b5+1*a5010x=8*d5+4*c5+2*b5+1*a5011x=2*d5+1*c5，y=2*b5+1*a5100x=2*d5+1*c5，y=2*b5+1*a5101無(wú)操作110無(wú)操作111無(wú)操作led的實(shí)現(xiàn)程序見(jiàn)附錄A7led模塊程序仿真結(jié)果如圖3.11所示：圖3.11led仿真圖從仿真結(jié)果可以看出： 當(dāng)m=0，n=0，o=0時(shí)，選中的是偶數(shù)分頻，由于d5等于1，故分頻系數(shù)為8，3個(gè)數(shù)碼顯示的順序?yàn)?，不顯示，8。3.4.8mux51模塊的設(shè)計(jì)mux51模塊的作用是：根據(jù)輸入的信號(hào)，選擇輸出的信號(hào)是那種分頻形式，并點(diǎn)亮相應(yīng)的發(fā)光二極管。mux51模塊的實(shí)現(xiàn)程序見(jiàn)附錄A8mux51模塊程序仿真結(jié)果如圖3.12所示：圖3.12mux-51仿真圖從仿真結(jié)果可以看出：該仿真結(jié)果是通過(guò)設(shè)置e=1（第一種分頻選中），其結(jié)果為第一個(gè)發(fā)光二極管亮，y輸出第一種分頻。結(jié)論通過(guò)各種方式查閱大量資料，首先了解已經(jīng)很成熟的分頻技術(shù)，大致上都是先將不同分頻形式的分頻器列舉出來(lái)，然后創(chuàng)建一個(gè)模塊，將不同形式的分頻器集成在一起。本次設(shè)計(jì)不同于其他的分頻器設(shè)計(jì)，本設(shè)計(jì)繼承了將不同分頻集成在一起的思想，但是本設(shè)計(jì)完全運(yùn)用了模塊設(shè)計(jì)，并且通過(guò)按鈕，撥碼開(kāi)關(guān)可以選擇分頻器和分頻系數(shù)，做到隨意的變頻。而數(shù)碼管則可以顯示分頻的系數(shù)，發(fā)光二極管則可以顯示何種分頻器讓人一幕了然。本課題大大降低了分頻工作的工作量，方便了分頻器的使用。本設(shè)計(jì)還有不足之處，分頻系數(shù)設(shè)置的小，導(dǎo)致分頻系數(shù)的輸入存在局限性，而時(shí)鐘頻率設(shè)置的較小，導(dǎo)致輸出頻率低。通過(guò)改變分頻系數(shù)的設(shè)置和調(diào)高時(shí)鐘頻率從而擴(kuò)大分頻系數(shù)的輸入圍提高輸出頻率。致本次設(shè)計(jì)，在萬(wàn)里老師的幫助下順利的完成了設(shè)計(jì)，在設(shè)計(jì)的過(guò)程中，老師給我提了很多的設(shè)計(jì)思想和一些資料，剛開(kāi)始的時(shí)候，我只會(huì)設(shè)計(jì)單一功能的分頻器，后來(lái)在老師的幫助下完成了本次設(shè)計(jì)，讓我有了進(jìn)一步學(xué)習(xí)設(shè)計(jì)的機(jī)會(huì)。再此要萬(wàn)里老師給予的幫助，如果沒(méi)有老師的幫助，這次設(shè)計(jì)很難完成。參考文獻(xiàn)[1]擦光輝.CPLD/TPGA的開(kāi)發(fā)與應(yīng)用[M].：電于工業(yè)，2002.[2]吳玉呂，胡水強(qiáng)，王文娟.基于CPLD/FPGA的多功能分頻器的設(shè)計(jì)與實(shí)現(xiàn)[L].世界電子元器件，2007(03).[3]松,黃繼業(yè).EDA技術(shù)實(shí)用教程（第三版）[M].：科學(xué),2006.[4]何賓.EDA原理與應(yīng)用.：清華大學(xué)，2010.[5]洪偉，袁斯華.基于QuartusII的FPGA/CPLD設(shè)計(jì).：電子工業(yè)，2006.[6]ALTERA，IntroductiontoQuartusⅡ，2007.[7]靜亞.FPGA系統(tǒng)設(shè)計(jì)中資源分配的分析和研究[J].信息化研究,2009,35(3):37239.[8]聶小燕.數(shù)字電路EDA設(shè)計(jì)與應(yīng)用.：人民郵電，2010.[9]白雪皎．基于CPLD半整數(shù)分頻器的設(shè)計(jì)[J]．大學(xué)學(xué)報(bào)，2006，116(1)：13—15．[10]雅興.FPGA原理、設(shè)計(jì)與應(yīng)用，大學(xué)，2005.[11]RobertK.Dueck編著.數(shù)字系統(tǒng)設(shè)計(jì)：CPLD應(yīng)用與VHDL編程，清華大學(xué)，2006[12]LiuYanfei，SenPC.DigitalControlofSwitchingPowerConverters.IEEEConferenceonControlApplicationsToronto，Canada，August.28-31,2005:635-640.附錄AVHDL源程序附錄A1：偶數(shù)分頻實(shí)現(xiàn)的程序libraryieee;useieee.std_logic_1164.all;entityfenpin_eisport(clkin,rst:instd_logic;a,b,c,d:inintegerrange1downto0;sel:instd_logic;clkout:outstd_logic);endfenpin_e;architecturertloffenpin_eissignaltemp:integerrange16downto0;signalcount:integerrange16downto0;begincount<=8*d+4*c+2*b;process(clkin)begin ifrst='1'then if(sel='1')then if(clkin'eventandclkin='1')then iftemp=count-1then temp<=0; else temp<=temp+1; endif; endif; else null; endif; else null; endif;endprocess;process(temp)begin ifrst='1'then if(sel='1')then iftemp<count/2then clout<='1'; else clout<='0'; endif; else null; endif; else clout<='0'; endif;endprocess;endrtl;附錄A2奇數(shù)分頻實(shí)現(xiàn)的程序libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfenpin_oisport(clk,rst:instd_logic;sel:instd_logic;a2,b2,c2,d2:inintegerrange1downto0;clkout1:outstd_logic);endfenpin_o;architecturertloffenpin_oissignalp,q,count1:integerrange18downto0;begincount1<=8*d2+4*c2+2*b2+1*a2;process(clk)begin ifrst='1'then if(sel='1')then if(clk'eventandclk='1')then ifp=count1-1then p<=0; else p<=p+1; endif; endif; else null; endif; else p<=count1-1; endif;endprocess;process(clk)begin ifrst='1'then if(sel='1')then if(clk'eventandclk='0')then ifq=count1-1then q<=0; else q<=q+1; endif; endif; else null; endif; else q<=count1-1; endif;endprocess;clkout1<='1'whenp<(count1-1)/2orq<(count1-1)/2else'0';endrtl;附錄A3半整數(shù)分頻實(shí)現(xiàn)的程序libraryieee;useieee.std_logic_1164.all;useieee.numeric_std.all;useieee.std_logic_unsigned.all;entityfenpin_misport(clkin,rst:instd_logic;sel:instd_logic;a3,b3,c3,d3:inintegerrange1downto0;clkout3:bufferstd_logic);endfenpin_m;architecturertloffenpin_missignalclk,div2:std_logic;signalcount:integerrange0to16;signalset:integerrange16downto0;beginset<=8*d3+4*c3+2*b3+1*a3;clk<=clkinxordiv2;process(clk)begin ifrst='1'then ifsel='1'then if(clk'eventandclk='1')then if(count=0)then count<=set-1; clkout3<='1'; else count<=count-1; clkout3<='0'; endif; endif; else count<=1; endif; else null; endif;endprocess;process(clkout3)begin ifsel='1'then if(clkout3'eventandclkout3='1')then div2<=notdiv2; endif; else null; endif;endprocess;endrtl;附錄A4占空比可調(diào)的分頻實(shí)現(xiàn)的程序libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.numeric_std.all;useieee.std_logic_unsigned.all;entityfenpin_hisport(clk,rst:instd_logic;sel:instd_logic;a4,b4,c4,d4:inintegerrange1downto0;clkout2:outstd_logic);endfenpin_h;architecturertloffenpin_hissignaltemp,m1,n1:integerrange5downto0;beginm1<=2*d4+1*c4;n1<=2*b4+1*a4;process(clk,temp,sel)beginifrst='1'then ifsel='1'then ifrising_edge(clk)then iftemp=n1-1then temp<=0; else temp<=temp+1; endif; endif; else null; endif;else temp<=n1-1;endif;endprocess;clkout2<='1'whentemp<m1else'0';endrtl;附錄A5小數(shù)分頻實(shí)現(xiàn)的程序libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfenpin_xisport( clkin:instd_logic; rst:instd_logic; sel1:instd_logic; a,b,c,d:inintegerrange1downto0; clk_out:outstd_logic );endfenpin_x;architecturearchoffenpin_xiscomponentnumberport( n:instd_logic_vector(3downto0); number0:outstd_logic_vector(3downto0); number1:outstd_logic_vector(3downto0) );endcomponent;componentfdnport( clock_in:instd_logic; enable:instd_logic; n_of_fd:instd_logic_vector(3downto0); clock_out:outstd_logic );endcomponent;componentselport( clock_in:instd_logic; Xnumber:instd_logic_vector(3downto0); sel_out:outstd_logic );endcomponent;componentmux1port( a:instd_logic; b:instd_logic; s:instd_logic; y:outstd_logic );endcomponent;signall:integerrange16downto0;signaln,x:std_logic_vector(3downto0);signalselt:std_logic;signalselt_not:std_logic;signalclock_1:std_logic;signalclock_2:std_logic;signalclock_sel:std_logic;signaln_fd:std_logic_vector(3downto0);signaln1_fd:std_logic_vector(3downto0);beginprocess(rst,sel1)begin ifrst='1'then ifsel1='1'then l<=8*d+4*c+2*b+a; else l<=4; endif; else l<=3; endif;endprocess;process(l)begin case(l)is when5=>n<="0001";x<="0001"; when6=>n<="0001";x<="0010"; when7=>n<="0001";x<="0011"; when9=>n<="0010";x<="0001"; when10=>n<="0010";x<="0010"; when11=>n<="0010";x<="0011"; when13=>n<="0100";x<="0001"; when14=>n<="0100";x<="0010"; when15=>n<="0100";x<="0011"; whenothers=>n<="0000";x<="0000"; endcase;endprocess;number0:numberportmap(n,n_fd,n1_fd);fdn0:fdnportmap(clkin,selt_not,n_fd,clock_1);fdnl:fdnportmap(clkin,selt,n1_fd,clock_2);mux21:mux1portmap(clock_2,clock_1,selt,clock_sel);sel0:selportmap(clock_sel,x,selt);selt_not<=notselt;clk_out<=clock_sel;endarch;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfdnisport( clock_in:instd_logic; enable:instd_logic; n_of_fd:instd_logic_vector(3downto0); clock_out:outstd_logic );endentity;architecturebhvoffdnissignalclock:std_logic;signalq0:std_logic;signalq1:std_logic;signalnumber:std_logic_vector(2downto0);signalcounter0:std_logic_vector(3downto0);signalcounter1:std_logic_vector(3downto0);beginfdn:process(enable,clock_in,n_of_fd,clock,q0,q1)beginnumber(2downto0)<=n_of_fd(3downto1); ifq1='0'then clock<=notclock_in; else clock<=clock_in; endif; if(enable='1')then if(n_of_fd(0)='0')then counter1<=(others=>'0'); q1<='0'; ifrising_edge(clock_in)then if(number="001")then q0<=notq0; else ifcounter0=number-1then counter0<=(others=>'0'); q0<=notq0; else counter0<=counter0+1; endif; endif; endif; else counter0<=(others=>'0'); q0<='0'; ifrising_edge(clock)then ifcounter1=numberthen counter1<=(others=>'0'); q1<=notq1; else counter1<=counter1+1; endif; endif; endif; else q0<='0'; q1<='0'; counter0<=(others=>'0'); counter1<=(others=>'0');endif;endprocessfdn;output:process(enable,n_of_fd(0),q0,q1)begin if(enable='1')then if(n_of_fd(0)='0')then clock_out<=q0; else clock_out<=q1; endif; else clock_out<='0'; endif;endprocessoutput;endbhv;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityselisport( clock_in:instd_logic; Xnumber:instd_logic_vector(3downto0); sel_out:outstd_logic );endentity;architecturebhvofselissignalXsubTen:std_logic_vector(3downto0);signalq:std_logic_vector(4downto0);beginXsubTen<=10-Xnumber;sel:process(clock_in,q)beginif(clock_in'eventandclock_in='0')then ifq+XsubTen>=10then q<=q+XsubTen-10; else q<=q+XsubTen; endif;endif;ifq>=Xnumberthen sel_out<='0';else sel_out<='1';endif;endprocesssel;endbhv;libraryieee;useieee.std_logic_1164.all;entitymux1isport( a:instd_logic; b:instd_logic; s:instd_logic; y:outstd_logic );endentity;architecturebhvofmux1isbeginwithsselecty<=awhen'1', bwhenothers;endbhv;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitynumberisport( n:instd_logic_vector(3downto0); number0:outstd_logic_vector(3downto0); number1:outstd_logic_vector(3downto0) );endentity;architecturebhvofnumberisbeginnumber0<=n;number1<=n+1;endbhv;附錄A6encoder_35模塊實(shí)現(xiàn)的程序libraryieee;useieee.std_logic_1164.all;entityencoder_35isport(p,q,v:instd_logic;a,b,c,d,e:outstd_logic);endencoder_35;architecturertlofencoder_35issignaltemp:std_logic_vector(2downto0);begintemp<=p&q&v;process(temp)begincasetempis when"000"=>e<='1';a<='0';b<='0';c<='0';d<='0'; when"001"=>d<='1';a<='0';b<='0';c<='0';e<='0'; when"010"=>c<='1';a<='0';b<='0';e<='0';d<='0'; when"011"=>b<='1';a<='0';e<='0';c<='0';d<='0'; when"100"=>a<='1';e<='0';b<='0';c<='0';d<='0'; whenothers=>a<='0';b<='0';c<='0';d<='0';e<='0';endcase; endprocess;endrtl;附錄A7led的實(shí)現(xiàn)程序libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityledisport(clk,rst,m,n,o:instd_logic;led_out:outstd_logic_vector(7downto0);led_bit:outstd_logic_vector(7downto0);a5,b5,c5,d5:inintegerrange1downto0);endled;architecturearchofledissignalf:std_logic_vector(2downto0);signalt_scan:std_logic_vector(1downto0);signaldata4,data5,data6,data7,data8:integerrange20downto0;signaldataout_xhdl1:std_logic_vector(7downto0);signalen_xhdl:std_logic_vector(7downto0);beginf<=m&n&o;data5<=8*d5+4*c5+2*b5+1*a5;led_out<=dataout_xhdl1;led_bit<=en_xhdl;process(a5,b5,c5,d5)begin ifrst='1'theniff="010"then data6<=data5-1;data7<=5; else iff="011"orf="100"then data6<=2*d5+c5;data7<=2*b5+a5; else if(data5>10)then data6<=1;data7<=data5-10; else data6<=0;data7<=data5; endif; endif; endif; else data6<=12;data7<=12; endif;endprocess;process(f)begin casefis when"011"=>data8<=10; when"100"=>data8<=11; when"010"=>data8<=11; whenothers=>data8<=12; endcase;endprocess;process(clk,rst)begin if(rst='0')then cnt_scan<="00";elsif(clk'eventandclk='1')then cnt_scan<=cnt_scan+1;endif;endprocess;process(cnt_scan)begin caset_scanis when"00"=>en_xhdl<="11111110"; when"01"=>en_xhdl<="11111101"; when"10"=>en_xhdl<="11111011"; whenothers=>null; endcase;endprocess;process(en_xhdl)begin caseen_xhdlis when"11111110"=>data4<=data7; when"11111101"=>data4<=data8; when"11111011"=>data4<=data6; whenothers=>null; endcase;endprocess;process(data4)begin casedata4iswhen0=>dataout_xhdl1<="11000000";when1=>dataout_xhdl1<="11111001";when2=>dataout_xhdl1<="10100100";when3=>dataout_xh