基于FPGA的VHDL語言溫度控制

..基于FPGA的恒溫控制系統(tǒng)孵化器是一種最新的孵化禽蛋的機(jī)器,通過人工制造適合禽蛋孵化的恒溫環(huán)境,來以較小的經(jīng)濟(jì)投入孵化禽蛋,通過調(diào)查,市面上的孵化器多數(shù)是以模擬電路的方式制造恒溫環(huán)境,如下圖這種模擬電路控制在實(shí)際應(yīng)用中很難做到恒溫控制,溫度會(huì)在最終歸的預(yù)設(shè)值附近上下浮動(dòng),影響禽蛋的孵化。而且,孵化器的溫度設(shè)置也是模擬電路,這樣是完全達(dá)不到精準(zhǔn)的溫度設(shè)置。通過學(xué)習(xí)FPGA,我設(shè)想運(yùn)用數(shù)字電路來對(duì)禽蛋孵化器內(nèi)部溫度進(jìn)行控制,來實(shí)現(xiàn)可控,可調(diào),溫度恒定的禽蛋孵化器。具體的設(shè)計(jì)框架如下通過前向溫度采集電路,采集當(dāng)前孵化器內(nèi)部的溫度信號(hào),將采集到的模擬信號(hào)通過ADC0809模數(shù)轉(zhuǎn)換芯片,轉(zhuǎn)變?yōu)镕PGA可控的數(shù)字信號(hào),FPGA芯片根據(jù)輸入的當(dāng)前實(shí)際溫度,控制輸出合理的數(shù)字信號(hào),再由DAC0832轉(zhuǎn)換為模擬信號(hào),輸入到后向加熱執(zhí)行電路,以此來完成對(duì)整個(gè)孵化器的溫度控制。整個(gè)系統(tǒng)中,帶有溫度傳感器的前向溫度采集電路作為系統(tǒng)的反饋環(huán)節(jié),實(shí)時(shí)反映當(dāng)前環(huán)境的具體溫度,具體的電路圖如下。前向溫度采集電路圖此電路設(shè)計(jì)以AD590作為溫度觸感器,通過添加相應(yīng)的調(diào)節(jié)電阻,讓溫度與輸出電壓保持一個(gè)相對(duì)線性的關(guān)系其中：為調(diào)零電阻為調(diào)滿度電阻最終得到的溫度與輸出電壓的關(guān)系式為：模數(shù)轉(zhuǎn)換芯片采用的是ADC0809,具體的連接電路圖如下IN0—IN7管角中任選一路作為前向溫度采集電路的輸入,VCC與同時(shí)接+5V電壓,與GND接地,OUT1—OUT8數(shù)據(jù)輸出端連接FPGA,START,OE,EOC,ADDA-C均連接FPGA,根據(jù)ADC0809的工作時(shí)序圖,由FPGA給出相應(yīng)的信號(hào)控制ADC0809。數(shù)模轉(zhuǎn)換部分采用的是DAC0832,具體連接圖如下DI0-DI7分別于FPGA的8位數(shù)據(jù)輸出端相連,因?yàn)镈AC0832工作在連續(xù)的負(fù)反饋電路中,故采用直通的工作方式,將WR1與WR2直接與地相連,ILE與CS,Xfer引腳均接至FPGA,有FPGA發(fā)送控制信號(hào)來控制DAC0832的工作。輸出引腳Iout1與Iout2連接一個(gè)流壓轉(zhuǎn)換器,將輸出的電流信號(hào)轉(zhuǎn)換為需要的電壓信號(hào),并進(jìn)行適當(dāng)?shù)姆糯?。最后輸出到孵化器的加熱電路。FPGA模塊控制ADC0809的工作狀態(tài),并接收來自ADC0809的數(shù)字信號(hào),與鍵盤輸入的預(yù)設(shè)信號(hào)進(jìn)行比較后,將控制信息傳送給DAC0832,經(jīng)由數(shù)模轉(zhuǎn)換器轉(zhuǎn)換后加在發(fā)熱裝置兩端,對(duì)整個(gè)孵化器內(nèi)部溫度進(jìn)行控制。整個(gè)的FPGA模塊分為以下幾個(gè)部分；分頻模塊：由于外界的時(shí)鐘源一般都較高,而ADC0809以及鍵盤掃描模塊需要的時(shí)鐘頻率較低,故需要對(duì)外界時(shí)鐘源進(jìn)行分頻,這里外界輸入時(shí)鐘源為20MHz,對(duì)其進(jìn)行64分頻。波形仿真圖如下：從波形圖可以看出,clk每經(jīng)過64個(gè)脈沖,clk1跳轉(zhuǎn)一次。分頻模塊工作正常；統(tǒng)計(jì)報(bào)告圖如下：分頻模塊的VHDL文件見附錄1.鍵盤模塊：鍵盤模塊的脈沖輸入來自分頻模塊。其中,輸入端口為兩位二進(jìn)制數(shù),分別接兩個(gè)按鍵,來對(duì)預(yù)設(shè)溫度進(jìn)行加減調(diào)控。輸出有兩個(gè)端口,xianshi端口作為保留端口,存儲(chǔ)著當(dāng)前預(yù)設(shè)溫度的數(shù)值,可外接顯示設(shè)備。zhi端口為信息傳送端口,其存儲(chǔ)值為當(dāng)前預(yù)設(shè)溫度值經(jīng)由采集電路溫度—電壓公式換算后的十進(jìn)制數(shù)值。換算公式如下：例：38攝氏度對(duì)應(yīng)的ADC0809輸出數(shù)據(jù)為5*38*256/100/5,得到十進(jìn)制值為97；波形仿真圖如下：圖〔1圖〔2圖中,shuru〔1為溫度減按鍵,shuru〔0為溫度加按鍵,相應(yīng)的預(yù)設(shè)溫度對(duì)應(yīng)相應(yīng)的ADC0809輸出值,由圖2得,當(dāng)預(yù)設(shè)溫度為38攝氏度時(shí),對(duì)應(yīng)換算后的ADC0809輸出數(shù)據(jù)為97,與計(jì)算相符。鍵盤輸入模塊工作正常。統(tǒng)計(jì)報(bào)告圖如下：鍵盤模塊的VHDL文件見附錄2.ADC0809控制模塊：經(jīng)查閱資料,DAC0832需采用直通式,故,將DAC0832的控制語句直接寫在了ADC0809的控制語句塊內(nèi)。ile為輸出到ADC0832的輸入鎖存允許信號(hào),cont為ADC0832WR1,WR2,CS等引腳。Wendu為預(yù)設(shè)溫度的輸入引腳。din為ADC0809轉(zhuǎn)換后的輸出信號(hào),dout為受FPGA控制的輸出到DAC0832的控制信號(hào)。clk8為來自為頻器的時(shí)鐘信號(hào)。根據(jù)ADC0809的時(shí)序圖,總結(jié)出相應(yīng)的狀態(tài)轉(zhuǎn)移圖,一次來編寫控制ADC0809的VHDL語言文件,狀態(tài)轉(zhuǎn)移圖如下：具體波形仿真圖如下：波形仿真建立在預(yù)設(shè)溫度為38攝氏度的條件下。前面提到,38攝氏度對(duì)應(yīng)的ADC0809輸出值為97,VHDL程序中設(shè)定,當(dāng)ADC0809輸入值大于或等于97時(shí)〔當(dāng)前溫度大于或等于預(yù)設(shè)溫度,FPGA輸出到DAC0832的控制信號(hào)為0,即停止加熱。當(dāng)ADC0809輸入值小于92〔即36攝氏度,與設(shè)定溫度相差大于兩度時(shí),FPGA輸出到DAC0832的控制信號(hào)為255,即以最大功率加熱。當(dāng)ADC0809輸入值小于92時(shí),將會(huì)細(xì)分為5個(gè)階段,即以逐次遞減的功率加熱。由圖可知,ADC0809工作正常。統(tǒng)計(jì)報(bào)告圖如下：ADC0809模塊的VHDL仿真文件見附錄3.最后,將三個(gè)模塊運(yùn)用元件例化語句連接在一塊,并進(jìn)行電路觀察,生成相應(yīng)的邏輯電路,如下圖：總體波形仿真如下圖波形分析：剛開始,FPGAjia置1,預(yù)設(shè)溫度逐漸增加,如下圖當(dāng)溫度到達(dá)38攝氏度后停止增加,即將38攝氏度作為預(yù)設(shè)溫度,隨后,觀察FPGAin與FPGAout。當(dāng)預(yù)設(shè)溫度為38攝氏度時(shí),輸入為97時(shí),對(duì)應(yīng)輸出為0,當(dāng)為92時(shí),對(duì)應(yīng)輸出為5,當(dāng)為96時(shí),對(duì)應(yīng)輸出為1,當(dāng)輸入不在92-97之間,輸入大于97時(shí),輸出為0,輸入小與92時(shí),輸出為255.觀察上圖波形仿真,完全符合程序設(shè)計(jì)。后面給FPGAjian置1,預(yù)設(shè)溫度會(huì)隨之降低。統(tǒng)計(jì)報(bào)告圖如下：總體的VHDL程序見附錄4.附錄1：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;entityfenpinisport<clk:instd_logic;--外部輸入時(shí)鐘源clk1:outstd_logic>;endfenpin;--分頻后的時(shí)鐘源architectureboffenpinissignalcount:std_logic_vector<7downto0>;--信號(hào)定義signalclk2:std_logic;beginprocess<clk>beginif<clk'eventandclk='1'>then--計(jì)數(shù)脈沖上升沿if<count="01000000">thencount<=<others=>'0'>;clk2<=notclk2;--當(dāng)達(dá)到64個(gè)脈沖時(shí)count置0,clk2取反elsecount<=count+1;--未達(dá)到64脈沖時(shí)繼續(xù)計(jì)數(shù)；endif;endif;clk1<=clk2;——將產(chǎn)生的分頻信號(hào)給輸出端口endprocess;endb;附錄2：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityjianpanisport<clk:instd_logic;--分頻后的時(shí)鐘輸入shuru:instd_logic_vector<1downto0>;--輸入端,按鍵加0位,按鍵減1位zhi:outinteger;--預(yù)設(shè)溫度轉(zhuǎn)化為ADC0809輸出值xianshi:outinteger>;--當(dāng)前預(yù)設(shè)溫度endentity;architecturebehaofjianpanissignalx:integerrange0to200;--定義信號(hào)beginprocess<clk>beginif<clk'eventandclk='1'>thencaseshuruis--檢測(cè)是否有輸入when"01"=>x<=x+1;--按鍵加按下,溫度+1when"10"=>if<x=0>thenx<=0;--按鍵減按下,判斷溫度是否為0elsex<=x-1;--若為0,則依舊為0,否則,溫度-1endif;whenothers=>x<=x;--其他按鍵情況,溫度不變endcase;endif;xianshi<=x;--將溫度賦給顯示輸出端zhi<=x*5*256/100/5;--將溫度轉(zhuǎn)化后賦給輸出端endprocess;endbeha;附錄3：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityADC0809isport<din:instd_logic_vector<7downto0>;--ADC0809輸出的采樣數(shù)據(jù)clk8:instd_logic;--時(shí)鐘信號(hào)eoc:instd_logic;--ADC0809轉(zhuǎn)換結(jié)束指示,高電平有效ale:outstd_logic;--ADC0809地址鎖存次信號(hào)ile:outstd_logic;--DAC0832數(shù)據(jù)鎖存允許cont:outstd_logic;--DAC0832控制信號(hào)〔WR1,WR2,CS,Xferstart:outstd_logic;--ADC0809轉(zhuǎn)換啟動(dòng)信號(hào)oe:outstd_logic;--ADC0809數(shù)據(jù)輸出允許信號(hào)wendu:ininteger;--溫度顯示adda:outstd_logic;--ADC0809信號(hào)通道控制位addb:outstd_logic;--ADC0809信號(hào)通道控制位addc:outstd_logic;--ADC0809信號(hào)通道控制位lock0:outstd_logic;--ADC0809觀察數(shù)據(jù)鎖存時(shí)鐘dout:outstd_logic_vector<7downto0>>;--輸出到DAC0832的8位數(shù)據(jù)endADC0809;architecturebehaofADC0809istypestatesis<st0,st1,st2,st3,st4>;--定義ADC0809工作狀態(tài)signalcurrent_state,next_state:states:=st0;--定義信號(hào)signalregl:std_logic_vector<7downto0>;signalshuchu:std_logic_vector<7downto0>;signallock:std_logic;signalcount:std_logic_vector<7downto0>;beginadda<='1';--地址輸入001,選擇IN1addb<='0';addc<='0';dout<=shuchu;-將處理后的數(shù)據(jù)傳輸?shù)捷敵龆丝趌ock0<=lock;--數(shù)據(jù)傳輸ile<='1';--DAC0832的控制信號(hào)cont<='0';com:process<current_state,eoc>--狀態(tài)轉(zhuǎn)移begincasecurrent_stateiswhenst0=>ale<='0';start<='0';lock<='0';oe<='0';next_state<=st1;whenst1=>ale<='1';start<='1';lock<='0';oe<='0';next_state<=st2;whenst2=>ale<='0';start<='0';lock<='0';oe<='0';next_state<=st1;if<eoc='1'>thennext_state<=st3;elsenext_state<=st2;endif;whenst3=>ale<='0';start<='0';lock<='0';oe<='1';next_state<=st4;whenst4=>ale<='0';start<='0';lock<='1';oe<='1';next_state<=st0;whenothers=>next_state<=st0;endcase;endprocesscom;reg:process<clk8>beginif<clk8'eventandclk8='1'>thencurrent_state<=next_state;--在時(shí)鐘上升沿改變狀態(tài)endif;endprocessreg;latch1:process<lock>beginiflock='1'andlock'eventthenregl<=din;--將輸入數(shù)據(jù)賦給中間變量endif;endprocesslatch1;kongzhi:process<regl>beginif<regl<wendu>then--判斷輸入數(shù)據(jù)與預(yù)設(shè)溫度的大小casewendu-reglis--判斷輸入數(shù)據(jù)與預(yù)設(shè)溫度的when"00000101"=>shuchu<="00000101";--差值為5時(shí)輸出控制信號(hào)5when"00000100"=>shuchu<="00000100";--差值為4時(shí)輸出控制信號(hào)4when"00000011"=>shuchu<="00000011";--差值為3時(shí)輸出控制信號(hào)3when"00000010"=>shuchu<="00000010";--差值為2時(shí)輸出控制信號(hào)2when"00000001"=>shuchu<="00000001";--差值為1時(shí)輸出控制信號(hào)1whenothers=>shuchu<="11111111";--差值大于5時(shí)輸出255endcase;elseshuchu<="00000000";--當(dāng)前溫度大于預(yù)設(shè)溫度,輸出0endif;endprocesskongzhi;endbeha;附錄4：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityFPGAisport<clkin:instd_logic;--定義外部時(shí)鐘端口FPGAeoc:instd_logic;FPGAin:instd_logic_vector<7downto0>;FPGAout:outstd_logic_vector<7downto0>;FPGAale:outstd_logic;FPGAjia:instd_logic;FPGAjian:instd_logic;FPGAwendu:outinteger;FPGAile:outstd_logic;FPGAcont:outstd_logic;FPGAstart:outstd_logic;FPGAoe:outstd_logic;FPGAadda:outstd_logic;FPGAaddb:outstd_logic;FPGAaddc:outstd_logic>;endentity;architecturebehaofFPGAiscomponentADC0809is--元件例化聲明port<din:instd_logic_vector<7downto0>;clk8:instd_logic;eoc:instd_logic;ale:outstd_logic;ile:outstd_logic;cont:outstd_logic;start:outstd_logic;wendu:ininteger;oe:outstd_logic;adda:outstd_logic;addb:outstd_logic;addc:outstd_logic;lock0:outstd_logic;dout:outstd_logic_vector<7downto0>>;endcomponent;componentfenpinis--元件例化聲明port<clk:instd_logic;clk1:outstd_logic>;endcomponent;componentjianpanisport<clk:instd_logic;shuru:instd_logic_vector<1downto0>;zhi:outinteger;xianshi:outinteger>;endcomponent;signalc:std_logic;--定義中間變量signaln:integer;beginU0:fenpinportmap<clk=>clkin,clk1=>c>;--元件例化U1:ADC0809portmap<clk8=>c,wendu=>n,din=>FPGAin,eoc=>FPGAeoc,dout=>FPGAout,ale=>FPGAale,ile=>FPGAile,cont=>FPGAcont,start=>FPGAstart,oe=>FPGAoe,adda=>FPGAadda,addb=>FPGAaddb,addc=>FPGAaddc>;U2:jianpanportmap<clk=>c,shuru<1>=>FPGAjian,shuru<0>=>FPGAjia,zhi=>n,xianshi=>FPGAwendu>;endbeha;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;entityfenpinisport<clk:instd_logic;--外部輸入時(shí)鐘源clk1:outstd_logic>;endfenpin;--分頻后的時(shí)鐘源architectureboffenpinissignalcount:std_logic_vector<7downto0>;--信號(hào)定義signalclk2:std_logic;beginprocess<clk>beginif<clk'eventandclk='1'>then--計(jì)數(shù)脈沖上升沿if<count="01000000">thencount<=<others=>'0'>;clk2<=notclk2;-當(dāng)達(dá)到64個(gè)脈沖時(shí)count置0,clk2取反elsecount<=count+1;--未達(dá)到64脈沖時(shí)繼續(xù)計(jì)數(shù)；endif;endif;clk1<=clk2;——將產(chǎn)生的分頻信號(hào)給輸出端口endprocess;endb;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityjianpanisport<clk:instd_logic;--分頻后的時(shí)鐘輸入shuru:instd_logic_vector<1downto0>;--輸入端,按鍵加0位,按鍵減1位zhi:outinteger;--預(yù)設(shè)溫度轉(zhuǎn)化為ADC0809輸出值xianshi:outinteger>;--當(dāng)前預(yù)設(shè)溫度endentity;architecturebehaofjianpanissignalx:integerrange0to200;--定義信號(hào)beginprocess<clk>beginif<clk'eventandclk='1'>thencaseshuruis--檢測(cè)是否有輸入when"01"=>x<=x+1;--按鍵加按下,溫度+1when"10"=>if<x=0>thenx<=0;--按鍵減按下,判斷溫度是否為0elsex<=x-1;--若為0,則依舊為0,否則,溫度-1endif;whenothers=>x<=x;--其他按鍵情況,溫度不變endcase;endif;xianshi<=x;--將溫度賦給顯示輸出端zhi<=x*5*256/100/5;--將溫度轉(zhuǎn)化后賦給輸出端endprocess;endbeha;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityADC0809isport<din:instd_logic_vector<7downto0>;--ADC0809輸出的采樣數(shù)據(jù)clk8:instd_logic;--時(shí)鐘信號(hào)eoc:instd_logic;--ADC0809轉(zhuǎn)換結(jié)束指示,高電平有效ale:outstd_logic;--ADC0809地址鎖存次信號(hào)ile:outstd_logic;--DAC0832數(shù)據(jù)鎖存允許cont:outstd_logic;--DAC0832控制信號(hào)〔WR1,WR2,CS,Xferstart:outstd_logic;--ADC0809轉(zhuǎn)換啟動(dòng)信號(hào)oe:outstd_logic;--ADC0809數(shù)據(jù)輸出允許信號(hào)wendu:ininteger;--溫度顯示adda:outstd_logic;--ADC0809信號(hào)通道控制位addb:outstd_logic;--ADC0809信號(hào)通道控制位addc:outstd_logic;--ADC0809信號(hào)通道控制位lock0:outstd_logic;--ADC0809觀察數(shù)據(jù)鎖存時(shí)鐘dout:outstd_logic_vector<7downto0>>;--輸出到DAC0832的8位數(shù)據(jù)endADC0809;architecturebehaofADC0809istypestatesis<st0,st1,st2,st3,st4>;--定義ADC0809工作狀態(tài)signalcurrent_state,next_state:states:=st0;--定義信號(hào)signalregl:std_logic_vector<7downto0>;signalshuchu:std_logic_vector<7downto0>;signallock:std_logic;signalcount:std_logic_vector<7downto0>;beginadda<='1';--地址輸入001,選擇IN1addb<='0';addc<='0';dout<=shuchu;--將處理后的數(shù)據(jù)傳輸?shù)捷敵龆丝趌ock0<=lock;--數(shù)據(jù)傳輸ile<='1';--DAC0832的控制信號(hào)cont<='0';com:process<current_state,eoc>--