(完整版)EDA期末考試題06

第第頁共5頁七、綜合題（20分）用VHDL設(shè)計兩層升降平臺控制器圖a是一個兩層的升降平臺示意圖，一層和二層各有一個按鈕用來呼叫升降機。問題1,請完成cntlOO模塊的VHDL設(shè)計（實體部分已給出，不用寫），參考的仿真波形如圖c所示。HiIIIIIIIIIIIIIIIIIIIITT|!!!!!!!!!!!!!!!!HHT第二層圖ccntlOO仿真波形圖ArchitectureoneofcntlOOisBeginProcess(clk,en)Variableq:std_logic_vector(7downto0);BeginIfen=‘0'thenq:=(others=>‘0');Elsifclk'eventandclk=‘1'thenq:=q+1;Endif;Ifq<“01100100”thencout<=‘0';Elsecout<=‘1';Endif;Endprocess;Endone;第一層圖a兩層升降平臺示意圖對應(yīng)圖a的升降平臺控制器，擬用VHDL語言設(shè)計一個電路模擬其控制邏輯，圖b為該VHDL電路的設(shè)計模塊圖。doorupdowncntlOOenelev2coutJ!/2/2clkrstcallarr圖b兩層升降平臺控制器設(shè)計模塊圖圖b中的cntlOO模塊用來控制升降臺開關(guān)門延時，elev2為升降平臺狀態(tài)控制器。升降臺閘門由打開到關(guān)閉或由關(guān)閉到打開時，elev2模塊向cntlOO模塊輸出一個en計數(shù)使能信號（高電平有效）。cntlOO模塊計數(shù)溢出（三lOO）時cntlOO輸出cout信號為高電平，同時cntlOO計數(shù)停止。cntlOO模塊的實體描述如下所示：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT100ISPORT（CLK,EN:INSTD_LOGIC;--時鐘、使能信號COUT:OUTSTD_LOGIC）;--溢出信號ENDCNT100:問題2,以下是elev2模塊的VHDL描述:請根據(jù)elev2的VHDL描述畫出其狀態(tài)遷移圖。libraryieee;useieee.std_logic_1164.all;entityelev2isport(clk,coutcallarrdoorup:downenrst:instd_logic;--時鐘、復(fù)位信號:instd_logic;--定時溢出信號:instd_logic_vector(2downto1);--呼叫信號:instd_logic_vector(2downto1);--至U達信號:outstd_logic;outstd_logic;:outstd_logic;outstd_logic);—門控信號，低電平開門—上升信號一一下降信號--延時計數(shù)清零、使能信號architecturebehavconstantCL1:constantOP1:constantUP1:constantDN2:constantCL2:constantOP2:endelev2;ofelev2isstd_logic_vector(2std_logic_vector(2std_logic_vector(2std_logic_vector(2std_logic_vector(2std_logic_vector(2downtodowntodowntodowntodowntodownto0)0)0)0)0)0)"000";--一樓關(guān)門"100";--一樓開門"010";--一樓上升"001";--二樓下降"011";--二樓關(guān)門"111";--二樓開門UP1BEE(2)rLrcall(1)/=rl'call,Fr|i|CL20P2CL1n-callCl)■*caLL(2)11DN2SEE：L)/=rl'irr(1)=f11call=rl1andcalL(l]-'rglim匸T1'Mil(2：i/=rlrcall⑵n

呂mdcaLLCD-^l^:std_logic_vector(2downto0);一一狀態(tài)控制信號signalcontrolbegindoor<=notcontrol(2);up<=control(1);down<=control(0);process(clk,rst,arr,call)variableven:std_logic;beginifrst='1'thenelsifclk'eventandis問題3,根據(jù)圖b所示升降平臺模塊圖，寫出升降平臺控制器ELEV_TOP的VHDL頂層描述:casecontrolCL1when=>whenOP1=>control<=CL1;clk='1'thenifcout='1'then--關(guān)門已完畢ifcall(1)='1'thencontrol<=elsifcall(2)='1'thencontrolelsecontrol<=CL1;en<='1';elsecontrol<=CL1;en<='1';ifcout='1'then--開門已完畢ifcall(1)='1'thencontrol<=OP1;en<=OP1;en<=<=UP1;enendif;endif;elsecontrolelsecontrol<=<=CL1;en<='0';endif;endif;OP1;en<='1';whenUP1=>ifarr(2)='1'thencontrol<=CL2;elsecontrol<=UP1;endif;whenDN2=>ifarr(1)='1'thencontrol<=CL1;elsecontrol<=DN2;endif;whenCL2=>ifcout='1'then--關(guān)門已完畢whenOP2=>whenothersifcall(2)='1'thencontrol<=elsifcall(1)='1'thencontrolelsecontrol<=CL2;en<='1';elsecontrol<=CL2;en<='1';ifcout='1'then--開門已完畢ifcall(2)='1'thencontrol<=elsecontrol<=CL2;en<='0';elsecontrol<=OP2;en<='1';=>ifarr(10=‘1'thencontrol<=

elsecontrol<=CL2;endif;OP2;en<=<=DN2;enendif;endif;OP2;en<=endif;endif;CL1;'0';<='1';'1'；'0';<='1';'1'；endcase;endif;endprocess;endbehav;Port(clk,rst:instdlogic;Call,arr:instdlogicvector(2downto1);Door,up,down:outstdlogic);Endelev;ArchitectureoneofeleviscomponentCNT100PORT(CLK,EN:INSTDLOGIC;--時鐘、使能信號COUT:OUTSTD_LOGIC);--溢出信號ENDcomponent;componentelev2isport(clk,rst:instdlogic;--時鐘、復(fù)位信號cout:instdlogic;--定時溢出信號call:instdlogicvector(2downto1);--呼叫信號arrinstdlogicvector(2downto1);--至U達信號door:outstdlogic;--門控信號，低電平開門up:outstdlogic;--上升信號down:outstdlogic;—下降信號en:outstdlogic);--延時計數(shù)清零、使能信號endcomponent;sign