計(jì)算機(jī)組織與結(jié)構(gòu)：chapter8

DigitalIntegratedCircuits

ADesignPerspectiveDesign

MethodologiesJanM.RabaeyAnanthaChandrakasanBorivoje

NikolicDecember10,2002TheDesignProductivityChallengeSource:sematech97Agrowinggapbetweendesigncomplexityanddesignproductivity1981LogicTransistorsperChip(K)Productivity(Trans./Staff-Month)19831985198719891991199319951997199920012003200520072009ASimpleProcessorMEMORYDATAPATHCONTROLINPUT-OUTPUTINPUT/OUTPUTASystem-on-a-Chip:ExampleCourtesy:PhilipsImpactofImplementationChoicesEnergyEfficiency(inMOPS/mW)Flexibility

(orapplicationscope)0.1-11-1010-100100-1000NoneFullyflexibleSomewhatflexibleHardwiredcustomConfigurable/ParameterizableDomain-specificprocessor(e.g.DSP)EmbeddedmicroprocessorDesignMethodologyDesignprocesstraversesiterativelybetweenthreeabstractions:

behavior,structure,andgeometryMoreandmoreautomationforeachofthesestepsImplementationChoicesCustomStandardCellsCompiledCellsMacroCellsCell-basedPre-diffused(GateArrays)Pre-wired(FPGA's)Array-basedSemicustomDigitalCircuitImplementationApproachesTheCustomApproachIntel4004CourtesyIntelTransitiontoAutomationandRegularStructuresIntel4004(‘71)Intel8080Intel8085Intel8286Intel8486CourtesyIntelCell-basedDesign(orstandardcells)RoutingchannelrequirementsarereducedbypresenceofmoreinterconnectlayersStandardCell—Example[Brodersen92]StandardCell–TheNewGenerationCell-structurehiddenunder

interconnectlayersStandardCell-Example3-inputNANDcell(fromSTMicroelectronics):C=LoadcapacitanceT=inputrise/falltimeAutomaticCellGenerationCourtesyAcadabraInitialtransistorgeometriesPlaced

transistorsRouted

cellCompacted

cellFinishedcellAHistoricalPerspective:thePLAx0x1x2ANDplanex0x1x2ProducttermsORplanef0f1Two-LevelLogicInvertingformat(NOR-NOR)moreeffectiveEverylogicfunctioncanbe

expressedinsum-of-products

format(AND-OR)mintermPLALayout–ExploitingRegularityVDDGNDfAnd-PlaneOr-PlaneBreathingSomeNewLifeinPLAsRiverPLAsAcascadeofmultiple-output

PLAs.AdjacentPLAsareconnectedviariverrouting.Noplacementandroutingneeded.Outputbuffersandtheinputbuffersofthenextstageareshared.CourtesyB.BraytonExperimentalResultsLayoutofC2670NetworkofPLAs,4layersOTCRiverPLA,2layersnoadditionalroutingStandardcell,2layerschannelroutingStandardcell,3layersOTCArea:RPLAs(2layers) 1.23SCs(3layers)- 1.00,NPLAs(4layers) 1.31DelayRPLAs 1.04SCs 1.00NPLAs 1.09Synthesistime:forRPLA,synthesistimeequalsdesigntime;SCsandNPLAsstillneedP&R.Also:RPLAsareregularandpredictableMacroModules25632(or8192bit)SRAMGeneratedbyhard-macromodulegenerator“Soft”MacroModulesSynopsys

DesignCompiler“IntellectualProperty”AProtocolProcessorforWirelessSemicustomDesignFlowHDLLogicSynthesisFloorplanningPlacementRoutingTape-outCircuitExtractionPre-LayoutSimulationPost-LayoutSimulationStructuralPhysicalBehavioralDesignCaptureDesignIterationThe“DesignClosure”P(pán)roblemCourtesySynopsysIterativeRemovalofTimingViolations(whitelines)IntegratingSynthesiswith

PhysicalDesignPhysicalSynthesisRTL(Timing)ConstraintsPlace-and-Route

OptimizationArtworkNetlistwithPlace-and-RouteInfoMacromodulesFixednetlistsPre-diffused(GateArrays)Pre-wired(FPGA's)Array-basedLate-BindingImplementationGateArray—Sea-of-gatesUncommitedCellCommittedCell

(4-inputNOR)Sea-of-gatePrimitiveCellsUsingoxide-isolationUsinggate-isolationExample:BaseCellofGate-IsolatedGAFromSmith97Example:Flip-FlopinGate-IsolatedGAFromSmith97Sea-of-gatesRandomLogicMemorySubsystemLSILogicLEA300K(0.6mmCMOS)CourtesyLSILogicThereturnofgatearrays?metal-5metal-6Via-programmablecross-pointprogrammableviaViaprogrammablegatearray

(VPGA)[Pileggi02]ExploitsregularityofinterconnectPrewiredArraysClassificationofprewiredarrays(orfield-programmabledevices):BasedonProgrammingTechniqueFuse-based(program-once)Non-volatileEPROMbasedRAMbasedProgrammableLogicStyleArray-BasedLook-upTableProgrammableInterconnectStyleChannel-routingMeshnetworksFuse-BasedFPGAantifuse

polysiliconONOdielectricn+

antifusediffusion2lFromSmith97Openbydefault,closedbyapplyingcurrentpulseArray-BasedProgrammableLogicPLAPROMPALI5I4O0I3I2I1I0O1O2O3ProgrammableANDarrayProgrammableORarrayI5I4O0I3I2I1I0O1O2O3ProgrammableANDarrayFixedORarrayIndicatesprogrammableconnectionIndicatesfixedconnectionO0I3I2I1I0O1O2O3FixedANDarrayProgrammableORarrayProgrammingaPROMf01X2X1X0f1NANA:programmednodeMoreComplexPALFromSmith97iinputs,jminterms/macrocell,kmacrocells2-inputmux

asprogrammablelogicblockFA0BS1ConfigurationABSF=00000X1X0Y1Y0YXXYX0YY0XY1XX1Y10X10Y1111XYXYXYLogicCellofActelFuse-BasedFPGALook-upTableBasedLogicCellLUT-BasedLogicCellCourtesyXilinxD4C1....C4xxxxxxD3D2D1F4F3F2F1LogicfunctionofxxxLogicfunctionofxxxLogicfunctionofxxxxxxx4xxxxxxxxxxxxxxxxxxxxxxxxxxxxxHPBitscontrolBitscontrolMultiplexerControlledbyConfigurationProgramxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxXilinx4000SeriesFiguremustbeupdatedArray-BasedProgrammableWiringInput/outputpinProgrammedinterconnectionInterconnectPointHorizontaltracksVerticaltracksCellMesh-basedInterconnectNetworkSwitchBoxConnectBoxInterconnect

PointCourtesyDehonandWawrzyniekTransistorImplementationofMeshCourtesyDehonandWawrzyniekHierarchicalMeshNetworkUseoverlayedmeshtosupportlongerconnectionsReducedfanoutandreduced

resistanceCourtesyDehonandWawrzyniekEPLDBlockDiagramMacrocellPrimaryinputsCourtesyAlteraAlteraMAXFromSmith97AlteraMAXInterconnectArchitectureLAB2PIALAB1LAB6tPIAtPIArowchannelcolumnchannelLABCourtesyAlteraArray-based(MAX3000-7000)Mesh-based(MAX9000)Field-ProgrammableGateArrays

Fuse-basedStandard-celllikefloorplanXilinx4000InterconnectArchitecture21284323CLB8484QuadSingleDoubleLongDirectConnectDirectConnectQuadLongGlobalClockLongDoubleSingleGlobalClockCarryChainLong1244CourtesyXilinxRAM-basedFPGAXilinxXC4000exCourtesyXilinxALow-EnergyFPGA(UCBerkeley)ArraySize:8x8(2x4LUT)PowerSupply:1.5V&0.8VConfiguration:MappedasRAMToggleFrequency:125MHzArea:3mmx3mmLargerGranularityFPGAs1-mm2-metal

CMOStech1.2x1.2mm2600ktransistors208-pinPGAfclock=50MHzPav

=3.6W@5VBasicModule:DatapathPADDI-2(UCBerkeley)Designatacrossroad

System-on-a-ChipRAM

500kGatesFPGA+1GbitDRAMPreprocessing

Multi-SpectralImagermCsystem+2GbitDRAMRecog-nition

Analog64SIMDProcessorArray+SRAMImageConditioning100GOPSEmbeddedapplicationswherecost,

performance,andenergyaretherealissues!DSPandcontrolintensiveMixed-modeCombinesprogrammableandapplication-specificmodulesSoftwareplayscrucialroleAddressingtheDesignComplexityIssue

ArchitectureReuseReusecomesingenerationsSource:TheoClaasen(Philips)–DAC00ArchitectureReUse

SiliconSystemPlatformFlexiblearchitectureforhardwareandsoftwareSpecific(programmable)componentsNetworkarchitectureSoftwaremodulesRulesandguidelinesfordesignofHWandSWHasbeensuccessfulinPC’sDominanceofafewplayerswhospecifyandcontrolarchitectureApplication-domainspecific(differenceinconstraints)Speed(computepower)DissipationCostsReal/non-realtimedataPlatform-BasedDesignAplatformisarestrictiononthespaceofpossibleimplementationchoices,providingawell-definedabstractionoftheunderlyingtechnologyfortheapplicationdeveloperNewplatformswillbedefinedatthearchitecture-micro-architectureboundaryTheywillbecomponent-based,andwillprovidearangeofchoicesfromstructured-customtofullyprogrammableimp