邊界掃描測(cè)試原理與應(yīng)用

1、Boundary Scan Overview邊界掃描測(cè)試測(cè)試原理與應(yīng)用Intelligent Boundary Scan SolutionsNo.1Boundary Scan Test測(cè)試之定義 所謂邊界(Boundary):係指IC腳端與內(nèi)部(功能邏輯閘)晶片間之接點(diǎn)。換言之進(jìn)行掃描測(cè)試IC腳端與晶片間之接點(diǎn)邊界，係所謂之邊界掃描測(cè)試。 1990年經(jīng)由IEEE 1149.1加以規(guī)格化之BST測(cè)試，俗稱為邊界掃描測(cè)試(Boundary Scan Test)2More Details on IEEE-1149.1= digital interconnection test IEEE-1149.4

2、= mixed-signal and analog interconnection test IEEE-1149.5= system level test IEEE-1149.6= Differential & AC coupled networks IEEE-1532 = In-System-Programming9/8/20223History of the Standard1985 JETAG (Joint European Test Action Group) 1986 JTAG (Europe and North America)1988 P1149 JTAG v2 (proposa

3、l)1990 IEEE Std 1149.1 -19901993 IEEE Std 1149.1a-19931994 IEEE Std 1149.1b-1994 (BSDL)2001 IEEE Std 1149.1 - 2001Terms synonyms with IEEE Std 1149.1Boundary Scan / BSCAN / BSTJTAG (Joint Test Action Group) 9/8/20224Boundary Scan Test測(cè)試之必要性5Boundary Scan Test測(cè)試之原理(二)若PCB印刷基板採(cǎi)用BScan測(cè)試相容元件時(shí)，最多僅需5條(通常為

4、4條)之專用線，即可測(cè)試:1. Test Data In (TDI )2. Test Data Out (TDO)3. Test Mode Select (TMS)4. Test Clock (TCK)5. Test Reset (TRST) =可以省略不用 *註=通常用六個(gè)Clock，當(dāng)作一個(gè)Reset 6Boundary Scan Test測(cè)試之原理(三)所謂測(cè)試存取埠:TAP(Test Access Port)=係指為進(jìn)行測(cè)試邏輯電路之指令，測(cè)試數(shù)據(jù)或測(cè)試結(jié)果等數(shù)據(jù)加入輸入/輸出之串列介面，上述4條信號(hào)線，經(jīng)由外界之電腦主機(jī)加以控制，以便執(zhí)行BScan測(cè)試。7Boundary Scan

5、Test測(cè)試之功能 元件之誤插接及臨近元件的短路測(cè)試 外界電路與元件間之輸入/輸出信號(hào)監(jiān)視 元件間之互接測(cè)試(Interconnecting Test) 可測(cè)試BGA元件之開路與短路作測(cè)試 Non-BGA IC腳的開路測(cè)試 可在板上燒錄資料(ISP) Flash / EEPROM (ISP) PLD / FPGA Devices 內(nèi)部邏輯電路之功能測(cè)試8Testbus SignalsTMS = Test Mode SelectTCK = Test ClockTDI = Test Data InTDO = Test Data OutTMSTCKTDOT A PT A PT A PBScan-de

6、viceBScan-deviceBScan-deviceTDITestbus interconnectionnonBScanICBScan netsIEEE-1149.1Bscan Cell 測(cè)試存取埠TAP = Test Access Port9/8/20229Standard DeviceCore LogicPinIEEE-1149.19/8/202210BScan DeviceTest Data Out(TDO)TCKCore LogicTest Access Port(TAP)Test Mode Select (TMS)Test Data In (TDI)Test Clock (TCK

7、) . some extra “intelligence” is needed for Test AccessBScan CellPinIEEE-1149.19/8/202211Test Access Port (TAP )測(cè)試存取埠TAP ControllerInstructions RegisterTDOTMSTDITCKBypass RegisterIDcode Register, opt.BScan Register310n000nMUXData RegisterIEEE-1149.19/8/202212IEEE-1532In-System ProgrammingProgramming

8、 devices (volatile or non-volatile)離散元件 mounted on a PCB through IEEE-1149.1 compliant TAP =PLD / FPGA Devices Programmable devices compliant to IEEE-1532 have a system mode and a test mode:System mode: differentiates 4 system modal states:Unprogrammed (在未寫入資料前)ISC Accessed (ISC Data file寫入)ISC Comp

9、lete (ISC Data file完成 )Operational (驗(yàn)證)Test mode :conform to IEEE-1149.19/8/202213ConclusionIEEE 1532 can be used for programming ofa single device on a device programmera single device in-systemmultiple devices concurrently in-systemStandard conform devices of different types from different vendors

10、 can be programmed concurrentlyProgramming algorithm and data are separatedIEEE-1532= In-System-Programming9/8/202214Integration with Flying Probe Tester(BScan+FPT)No.15What FPT Can TEST?類比元件的值ResistorCapacitorInductorTransistor臨近元件的短路測(cè)試Non-BGA IC腳的 開路測(cè)試上電後電壓/電流測(cè)試特性無(wú)治具 ICT 測(cè)試簡(jiǎn)易型AOI功能速度稍慢可涵蓋所有被動(dòng)零件測(cè)試短

11、路測(cè)試為選擇性考量16What Boundary Scan Can Test數(shù)位邏輯 IC 零件:（包含 BGA ）的開短路測(cè)試Boundary Scan IC ID檢查DRAM讀寫測(cè)試Flash , EEPROM 讀寫測(cè)試及資料在板燒錄(On Board programming) 特性：測(cè)試速度快（可在一分鐘之內(nèi)測(cè)完一片主機(jī)版）主要針對(duì)有提供 Boundary Scan IC 的量測(cè)主要針對(duì)開短路的製程問題做測(cè)試可分為做治具及不做治具的方法，治具成本遠(yuǎn)比 ICT 治具類便宜。(因測(cè)試點(diǎn)變少)17Boundary Scan Layout information邊界掃描測(cè)試相容線路設(shè)計(jì)需知Int

12、elligent Boundary Scan SolutionsNo.18 Boundary Scan Test測(cè)試之原理若PCB印刷基板採(cǎi)用BScan測(cè)試相容元件時(shí)，最多僅需5條(通常為4條)之專用線，即可測(cè)試:1. Test Data In (TDI )2. Test Data Out (TDO)3. Test Mode Select (TMS)4. Test Clock (TCK)5. Test Reset (TRST) =可以省略不用 *註=通常用六個(gè)Clock，當(dāng)作一個(gè)Reset 19I/O Interface，10PIN 100mil公的連接器PIN1TCKPIN2GNDPIN3TMSPIN4GNDPIN5TDOPIN6GNDPIN7TDIPIN8GNDPIN9TRSTPIN10NC板子上整個(gè)連接到 Boundary Scan 的介面連接器20TDITCKTMSTDOTDITDO串接方式為TMS,TCK,TRST並聯(lián)，TDI,TDO串聯(lián)21Boundary Scan controller 的連接器上的 TDI ，接到串接上第一個(gè) BS IC 的 TDI，第一個(gè) BS IC 的 TDO 接第二個(gè) IC 的 TDI，以此類推； 最後一個(gè) IC 的 TDO 則接連接器上的 TDO。